On Wed, 6 Feb 2019 12:12:27 -0800
Nanley Chery wrote:
> > + * For now, we can't enable OES_texture_view on Gen 7
> > because of
> > + * some piglit failures coming from
> > + * piglit/tests/spec/arb_texture_view/rendering-formats.c
> > that need
> > + * investigation.
> >
Various methods relating to resource management were previously marked
as kernel-specific, forcing them to stay downstream in the vendor
overlay and eventually be duplicated for DRM code. This patch adds back
this code in kernel-neutral space, allowing for code sharing and
minimising the diff to
Signed-off-by: Alyssa Rosenzweig
---
.../panfrost/midgard/midgard_compile.c| 28 +--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index
Most Midgard instructions take two-arguments logically; there are always
two arguments at the assembly level. For the few instructions that take
only a single argument, generally the second argument slot is unused,
with a zero inline constant occupying the space. fmov/imov are the
exception, where
For the series:
Reviewed-by: Marek Olšák
Marek
On Tue, Feb 5, 2019 at 9:14 PM Ilia Mirkin wrote:
> From: Karol Herbst
>
> If the driver does not support rendering to these formats but does
> support texturing, we can end up in incompatibilities between textures
> and renderbuffers that are
Regardless of whether the build uses kmsro, kmsro is the default driver
descriptor when the static loader is used. Thus, in an edge case where
the static loader is used, no static targets are loaded, and kmsro is
not compiled, a spurious warning is printed. There's no harm in
executing the stub
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_buffer.c | 56 ++--
src/gallium/drivers/radeonsi/si_dma_cs.c | 19
src/gallium/drivers/radeonsi/si_gfx_cs.c | 42 +++---
src/gallium/drivers/radeonsi/si_pipe.c | 23 ++
From: Marek Olšák
This is a no-op for drivers supporting persistent mappings.
---
src/mesa/state_tracker/st_atom_array.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_array.c
b/src/mesa/state_tracker/st_atom_array.c
index
Hi,
This patch series increases radeonsi performance in some cases.
glxgears performance decreases slightly.
Visible VRAM is usually congested due to CPU accesses, which cause
buffers to be evicted from that part of VRAM. This removes
the congestion for all data pushed into const_uploader.
We
From: Marek Olšák
radeonsi will require this. It's a no-op for drivers supporting persistent
mappings.
---
src/gallium/auxiliary/util/u_threaded_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
From: Marek Olšák
for radeonsi
---
src/gallium/auxiliary/util/u_upload_mgr.c | 33 ++-
src/gallium/auxiliary/util/u_upload_mgr.h | 4 +++
2 files changed, 31 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_upload_mgr.c
This patch is
Reviewed-by: Caio Marcelo de Oliveira Filho
On Wed, Feb 06, 2019 at 04:43:00PM -0600, Jason Ekstrand wrote:
> It's more clear and means we don't have to update the array every time
> we add an optional texture instruction argument
> ---
> src/intel/compiler/brw_fs_nir.cpp | 14
https://bugs.freedesktop.org/show_bug.cgi?id=109575
--- Comment #3 from LunarG ---
--Distro--
Ubuntu 16.04
--Kernel from Ubuntu's PPA--
https://kernel.ubuntu.com/~kernel-ppa/mainline/v4.10/
--GCC version--
gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
Compiled Mesa using autotools with
https://bugs.freedesktop.org/show_bug.cgi?id=109575
--- Comment #2 from Bas Nieuwenhuizen ---
Say I have a computer with similar GPU sitting around just for testing.
What would be the way to get to a similar software setup? What distro do you
use, what is your compiler, where did your kernel
It's more clear and means we don't have to update the array every time
we add an optional texture instruction argument
---
src/intel/compiler/brw_fs_nir.cpp | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
I have a patch series pending review to add support for pkg_config_path as a
-Doption (or in your native/cross file, if you like that better).
Quoting Tapani Pälli (2019-02-05 22:20:14)
>
>
> On 2/5/19 8:20 PM, Marek Olšák wrote:
> > PKG_CONFIG_PATH still seems to be forgotten by meson. Is
https://bugs.freedesktop.org/show_bug.cgi?id=109575
--- Comment #1 from LunarG ---
Possibly related to bug https://bugs.freedesktop.org/show_bug.cgi?id=109543
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
https://bugs.freedesktop.org/show_bug.cgi?id=109575
Bug ID: 109575
Summary: Mesa-19.0.0-rc1 : Computer Crashes trying to run
anything Vulkan
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: Linux
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 18 --
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 7 +++
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 0d2dab88317..b3dedef3d73 100644
---
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 31 ++-
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 +
2 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
From: Marek Olšák
wow, it's hard to believe that fence and syncobjs dependencies were ignored.
Cc: 18.3 19.0
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a059a3958d4..0d2dab88317 100644
---
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 86 +--
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 15 ++--
2 files changed, 42 insertions(+), 59 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
From: Marek Olšák
Cc: 18.3 19.0
---
src/gallium/auxiliary/util/u_threaded_context.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index 8e3bceae18d..b596c322918 100644
---
From: Marek Olšák
Cc: 18.3 19.0
---
src/gallium/drivers/radeonsi/si_buffer.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_buffer.c
b/src/gallium/drivers/radeonsi/si_buffer.c
index bac561de2cb..c01118ce96a 100644
---
Before reviewing this can we get a piglit test for the following scenario
Two "program" objects say:
1. vs->gs
2. fs
Where the interface between vs and gs has a used input that doesn't
exist in the vs. The test should fail validation, the idea being the
test would have failed on your v1 of
https://bugs.freedesktop.org/show_bug.cgi?id=109535
Timothy Arceri changed:
What|Removed |Added
Depends on||109561
Referenced Bugs:
On Sun, Feb 03, 2019 at 03:07:36PM +0200, Eleni Maria Stea wrote:
> OES_copy_image extension was disabled on Gen7 due to the lack of support
> for ETC2 images. Enabled it back. (Kenneth Graunke)
> ---
> src/mesa/drivers/dri/i965/intel_extensions.c | 18 ++
> 1 file changed, 14
Alyssa Rosenzweig writes:
> As kmsro allows an essentially mix-and-match hodgepodge of display
> drivers and renderonly GPUs, it doesn't make sense to couple the display
> driver entrypoint definition with the driver. Instead, we move *all*
> kmsro entrypoints to a shared kmsro block at the end
Split vl_compositor graphic shaders from vl_compositor API in order to share
vl_compositor API with vl_compositor compute shader later.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/Makefile.sources | 2 +
src/gallium/auxiliary/meson.build| 2 +
Add compute shader initilization, assign and cleanup in vl_compositor API.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/vl/vl_compositor.c | 31 ++-
src/gallium/auxiliary/vl/vl_compositor.h | 3 +++
2 files changed, 33 insertions(+), 1 deletion(-)
diff --git
Add debug option CS_COMPOSITOR_RENDER to enable/diable video
compositor compute shader render through system environment
Signed-off-by: James Zhu
---
src/gallium/auxiliary/vl/vl_compositor.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/vl/vl_compositor.c
Increase csc_matrix size to store more constants for compute shader.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/vl/vl_compositor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/vl/vl_compositor.c
b/src/gallium/auxiliary/vl/vl_compositor.c
Add video compute shader render. export CS_COMPOSITOR_RENDER=true
to enable video compute shader render.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/vl/vl_compositor.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/vl/vl_compositor.c
V2:
Split vl_compositor graphic shaders from vl_compositor API
replace compute_shader_sub_pic with compute_shader_rgba
Add VL_COMPOSITOR prefix in front of dirty define
replace backslashes in the commit title with forward slashes
James Zhu (7):
gallium/auxiliary/vl: Move dirty define to
Move dirty define to header file to share with compute shader.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/vl/vl_compositor.c | 15 ++-
src/gallium/auxiliary/vl/vl_compositor.h | 2 ++
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git
Add compute shader to support video compositor render.
Signed-off-by: James Zhu
---
src/gallium/auxiliary/Makefile.sources | 2 +
src/gallium/auxiliary/meson.build | 2 +
src/gallium/auxiliary/vl/vl_compositor.h| 1 +
src/gallium/auxiliary/vl/vl_compositor_cs.c | 408
On Sun, Feb 03, 2019 at 03:07:33PM +0200, Eleni Maria Stea wrote:
> The assertions that the GL_MAP_WRITE_BIT and GL_MAP_INVALIDATE_RANGE_BIT
> in intel_miptree_map_etc will fail when the ETC miptree is mapped for
> reading. As we are about to fix the GetCompressed* functions in the
> following
https://bugs.freedesktop.org/show_bug.cgi?id=109574
Bug ID: 109574
Summary: Blender 2.8
Product: Mesa
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity: normal
../src/gallium/drivers/freedreno/freedreno_resource.c: In function
‘fd_resource_create_with_modifiers’:
../src/gallium/drivers/freedreno/freedreno_resource.c:884:30: error:
‘DRM_FORMAT_MOD_QCOM_COMPRESSED’ undeclared (first use in this function)
allow_ubwc =
Quoting Eero Tamminen (2019-02-04 04:41:12)
> Hi,
>
> On 2.2.2019 3.20, Mark Janes wrote:
> > Eero Tamminen writes:
> >> On 31.1.2019 1.37, Dylan Baker wrote:
> >>> This email announces the mesa 19.0 release candidate 1. I'll keep this
> >>> email
> >>> fairly brief since I'm already running a
On Sun, Feb 03, 2019 at 03:59:42PM +0200, Eleni Maria Stea wrote:
> On Fri, 18 Jan 2019 17:09:03 -0800
> Nanley Chery wrote:
>
> > On Mon, Nov 19, 2018 at 10:54:08AM +0200, Eleni Maria Stea wrote:
> [...]
> > > + int img_d = smt->surf.logical_level0_px.depth;
> >
> > I don't think 3D ETC
On 2019-02-06 12:55 p.m., Tapani Pälli wrote:
> On 2/6/19 1:16 PM, Michel Dänzer wrote:
>> On 2019-02-05 11:30 p.m., Marek Olšák wrote:
>>> Hi,
>>>
>>> Video players request fbconfigs with these attributes:
>>> GLX_RED_SIZE = 8
>>> GLX_GREEN_SIZE = 8
>>> GLX_BLUE_SIZE = 8
>>> GLX_ALPHA_SIZE = 0
On Wed, 2019-02-06 at 10:33 -0500, Adam Jackson wrote:
> On Tue, 2019-02-05 at 17:30 -0500, Marek Olšák wrote:
>
> > If we expose 10-bit or 16-bit formats, a lot of software will be
> > broken. Any ideas how to get out of this rabbit hole?
>
> Use GLX_SGIX_visual_select_group to hide the
If there is no Static Use of an input variable, the linker shouldn't
fail whenever there is no defined matching output variable in the
previous stage.
From page 47 (page 51 of the PDF) of the GLSL 4.60 v.5 spec:
" Only the input variables that are statically read need to be
written by the
On Tue, 2019-02-05 at 17:30 -0500, Marek Olšák wrote:
> If we expose 10-bit or 16-bit formats, a lot of software will be
> broken. Any ideas how to get out of this rabbit hole?
Use GLX_SGIX_visual_select_group to hide the depth-30 formats after the
depth-24 ones. We're already doing this for
On Wed, 2019-02-06 at 09:42 +1100, Timothy Arceri wrote:
> On 6/2/19 1:11 am, Andres Gomez wrote:
> > On Fri, 2019-02-01 at 18:37 -0500, Ilia Mirkin wrote:
> > > On Fri, Feb 1, 2019 at 1:08 PM Andres Gomez wrote:
> > > > If there is no Static Use of an input variable, the linker shouldn't
> > > >
https://bugs.freedesktop.org/show_bug.cgi?id=109565
--- Comment #5 from Jakub Okoński ---
So I've duplicated the binding of that set into two separate bindings, one for
VERTEX stage, one for COMPUTE. And I updated them the same way:
Thread 0, Frame 0:
vkUpdateDescriptorSets(device,
https://bugs.freedesktop.org/show_bug.cgi?id=109565
--- Comment #4 from Jakub Okoński ---
If I try binding just the 2nd one, it does not crash and lets me submit that
command buffer to the compute queue. The problem must be with the first set
(called mvp_set in my app). It fails to bind in a
https://bugs.freedesktop.org/show_bug.cgi?id=109565
--- Comment #3 from Jakub Okoński ---
I'm not sure what you mean, I don't use any of the *_DYNAMIC variants of
DescriptorType.
This is how I define the layout of 2nd Descriptor Set I'm trying to bind in the
failing call:
https://bugs.freedesktop.org/show_bug.cgi?id=109565
--- Comment #2 from Samuel Pitoiset ---
Are you sure you use dynamic bindings correctly first?
Can you share a link to your custom app?
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
On Tuesday, 2019-02-05 15:19:46 +, Emil Velikov wrote:
> From: Emil Velikov
>
> The difference between the tree functions is the list of mandatory
> driver extensions. Pass that as an argument to the common helper.
>
> Signed-off-by: Emil Velikov
Pretty sure I also have this patch
https://bugs.freedesktop.org/show_bug.cgi?id=109565
--- Comment #1 from Jakub Okoński ---
This is on 19.0.0-rc2 compiled with --buildtype=debug, but debug symbols are
still missing? I'm not sure why that is the case.
--
You are receiving this mail because:
You are the QA Contact for the bug.
https://bugs.freedesktop.org/show_bug.cgi?id=109565
Bug ID: 109565
Summary: CmdBindDescriptorSets gets confused about dynamic
offsets
Product: Mesa
Version: unspecified
Hardware: Other
OS: All
Hi,
On 4.2.2019 14.41, Eero Tamminen wrote:
On 2.2.2019 3.20, Mark Janes wrote:
[...]
These regressions all need to be added to the release tracker. Thank
you for reporting them.
If that should track all the things regressed since previous
18.3 version was branched:
---
tag
https://bugs.freedesktop.org/show_bug.cgi?id=109535
Eero Tamminen changed:
What|Removed |Added
Depends on||109055
Referenced Bugs:
EXT_sRGB_write_control and EXT_texture_sRGB_R8 are now supported
on all drivers that support sRGB.
Signed-off-by: Gert Wollny
CC:
---
docs/relnotes/19.0.0.html | 2 ++
1 file changed, 2 insertions(+)
diff --git a/docs/relnotes/19.0.0.html b/docs/relnotes/19.0.0.html
index
On 2/6/19 1:16 PM, Michel Dänzer wrote:
On 2019-02-05 11:30 p.m., Marek Olšák wrote:
Hi,
Video players request fbconfigs with these attributes:
GLX_RED_SIZE = 8
GLX_GREEN_SIZE = 8
GLX_BLUE_SIZE = 8
GLX_ALPHA_SIZE = 0
Note that the values specify MINIMUM required component sizes, not exact
On Wed, Feb 6, 2019 at 11:46 AM Samuel Iglesias Gonsálvez <
sigles...@igalia.com> wrote:
> According to Vulkan spec, the new execution modes affect only
> correctly rounded SPIR-V instructions, which includes fadd,
> fsub and fmul.
>
> Signed-off-by: Samuel Iglesias Gonsálvez
> ---
>
On 2019-02-05 11:30 p.m., Marek Olšák wrote:
> Hi,
>
> Video players request fbconfigs with these attributes:
> GLX_RED_SIZE = 8
> GLX_GREEN_SIZE = 8
> GLX_BLUE_SIZE = 8
> GLX_ALPHA_SIZE = 0
>
> Note that the values specify MINIMUM required component sizes, not exact
> sizes. 10-10-10-2
https://bugs.freedesktop.org/show_bug.cgi?id=109535
Eero Tamminen changed:
What|Removed |Added
Depends on||108820
Referenced Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=109535
Eero Tamminen changed:
What|Removed |Added
Depends on||108787
Referenced Bugs:
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_device.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 6b272ecf558..3d5ffa641a0 100644
--- a/src/intel/vulkan/anv_device.c
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_extensions.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index defe263b2fb..fb8e9d593a3 100644
--- a/src/intel/vulkan/anv_extensions.py
+++
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index adc8bb4ddf5..1ee0e4d3e4e 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++
The remove_extra_rounding_modes() optimization will remove duplicated
rounding mode changes.
v2:
- Fix bug in the rounding mode change (Alejandro)
v3:
- Fix rounding modes.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 13 -
1 file changed, 12
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 809c7971c94..dfa6176340a 100644
--- a/src/intel/compiler/brw_fs.cpp
+++
According to the PRMs:
"The frc instruction computes, component-wise, the
truncate-to-minus-infinity fractional values of src0 and stores the
results in dst. The results, in the range of [0.0, 1.0], are the
fractional portion of the source data. The result is in the range
[0.0, 1.0] irrespective
We need this function to emit code that setups the control register later with
the defined execution mode for the shader.
v2:
- Fix bug in setting the default mode mask in brw_rnd_mode_from_nir()
- Fix support for rounding modes in brw_rnd_mode_from_nir()
Signed-off-by: Samuel Iglesias Gonsálvez
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 71e5a96e0a3..aab06a525bc 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index ef1ed9b7f0a..9dacff9785b 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++
The denorm mode is set in the control register, no need to do something else.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4 ---
src/intel/compiler/brw_eu_emit.c| 36 -
src/intel/compiler/brw_fs_generator.cpp | 13 +++--
3 files changed, 11 insertions(+), 42 deletions(-)
diff --git
v2:
- Fix bug in defining BRW_CR0_FP_MODE_MASK.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_eu.h | 4
src/intel/compiler/brw_eu_defines.h | 10 ++
src/intel/compiler/brw_eu_emit.c| 26 +
---
src/intel/compiler/brw_fs_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index aab06a525bc..86ab8c48135 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@
If we have fsin or fcos trigonometric operations with constant values as inputs,
we will multiply the result by 0.7 in brw_nir_apply_trig_workarounds,
making the result wrong. Running nir_opt_constant_folding before, we will
calculate correctly the result for these trignometric ops.
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes fadd,
fsub and fmul.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 17 +
1 file changed, 17 insertions(+)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_double_ops.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_lower_double_ops.c
b/src/compiler/nir/nir_lower_double_ops.c
index 4d4cdf635ea..525f2d19dc7 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index b0092bcb2ad..b62641f3db5 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 8128ed346af..b6036cf876e 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/Makefile.sources | 2 +
src/util/double.c | 197 ++
src/util/double.h | 46 +
src/util/meson.build | 2 +
4 files changed, 247 insertions(+)
create mode 100644
It adds round-towards-zero and round-to-nearest-even opcodes for
floating point conversions.
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes these conversions.
v2:
- Move code to nir_opcodes.py (Connor)
Signed-off-by: Samuel
Until now, it was using the floating point version of fmin/fmax,
instead of the double version.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opcodes.py
According to VK_KHR_shader_float_controls:
"Denormalized values obtained via unpacking an integer into a vector
of values with smaller bit width and interpreting those values as
floating-point numbers must: be flushed to zero, unless the entry point
is declared with the code:DenormPreserve
This way, we can implement its support later if SPIR-V supports it.
Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only
applies to f2f16 conversions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/intel/compiler/brw_fs_nir.cpp | 4
1 file changed, 4 insertions(+)
diff
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opt_algebraic.py | 73 +++
1 file changed, 73 insertions(+)
diff --git a/src/compiler/nir/nir_opt_algebraic.py
b/src/compiler/nir/nir_opt_algebraic.py
index 71c626e1b3f..3800db1da20 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index b62641f3db5..e9b1b0b8fec 100644
---
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes Fract.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_constant_expressions.py | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_constant_expressions.py
b/src/compiler/nir/nir_constant_expressions.py
index e79590f8359..0b3da1b21ac
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which is the case for ldexp.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_opcodes.py | 14 ++
1 file changed, 14 insertions(+)
diff --git
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index a6d2c5fdd07..b0092bcb2ad 100644
---
If x < 0 -> atan2(x, x) = -3*pi/4.
If x > 0 -> atan2(x, x) = pi/4.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_glsl450.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index e9b1b0b8fec..8128ed346af 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_alu.c | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 848fbbdb07c..881a9bab314 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/spirv/vtn_alu.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 881a9bab314..06320adf152 100644
---
v2:
- Fixed bug in rounding modes for conversion ops, it was not considering
the rounding mode of the destination data type.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir.h | 16
src/compiler/spirv/vtn_alu.c | 14 +-
2 files changed, 29
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_algebraic.py | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/compiler/nir/nir_algebraic.py
b/src/compiler/nir/nir_algebraic.py
index fe9d1051e67..9aa1b1928b8 100644
---
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/util/half_float.c | 74 +++
src/util/half_float.h | 7
2 files changed, 81 insertions(+)
diff --git a/src/util/half_float.c b/src/util/half_float.c
index 63aec5c5c14..5fdcb20045b 100644
---
According to Vulkan spec, the new execution modes affect only
correctly rounded SPIR-V instructions, which includes FaceForward.
FaceForward is lowered into fdot* instructions.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_builder.h | 32 +++
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