[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

2019-02-16 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=109535 Bug 109535 depends on bug 109581, which changed state. Bug 109581 Summary: [BISECTED] Nothing is Rendered on Sascha Willem's "subpasses" demo https://bugs.freedesktop.org/show_bug.cgi?id=109581 What|Removed

[Mesa-dev] [Bug 109656] duplicate symbol _compute_shader_video_buffer

2019-02-16 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=109656 Bug ID: 109656 Summary: duplicate symbol _compute_shader_video_buffer Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Mac OS X (All) Status: NEW

[Mesa-dev] [PATCH 1/2] panfrost: Cleanup mali_viewport (clipping) code

2019-02-16 Thread Alyssa Rosenzweig
Signed-off-by: Alyssa Rosenzweig --- .../drivers/panfrost/include/panfrost-job.h | 13 +++ src/gallium/drivers/panfrost/pan_context.c| 23 --- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/src/gallium/drivers/panfrost/include/panfrost-job.h

Re: [Mesa-dev] [PATCH v4 38/40] compiler/spirv: move the check for Int8 capability

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > So it is right after the checks for the other various Int* capabilities. > --- > src/compiler/spirv/spirv_to_nir.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH v4 33/40] intel/compiler: also set F execution type for mixed float mode in BDW

2019-02-16 Thread Jason Ekstrand
Matt, Curro, Could one of you please take a look at this and the other validator patches in this series? Region restrictions aren't my strongest area. On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > The section 'Execution Data Types' of 3D Media GPGPU volume, which > describes

[Mesa-dev] [PATCH v2 2/3] i965: Add INTEL_DEBUG=hang

2019-02-16 Thread Chris Wilson
Introduce a new debug option to wilfully cause the GPU to hang and for the kernel to accuse of being neglectful. --- src/intel/Makefile.sources| 2 + src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 1 +

Re: [Mesa-dev] [PATCH v4 23/40] intel/compiler: rework conversion opcodes

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 5:57 AM Iago Toral Quiroga wrote: > Now that we have the regioning lowering pass we can just put all of these > opcodes together in a single block and we can just assert on the few cases > of conversion instructions that are not supported in

Re: [Mesa-dev] [PATCH v4 13/40] intel/compiler: add instruction setters for Src1Type and Src2Type.

2019-02-16 Thread Jason Ekstrand
Acked-by: Jason Ekstrand On Tue, Feb 12, 2019 at 11:52 AM Iago Toral Quiroga wrote: > The original SrcType is a 3-bit field that takes a subset of the types > supported for the hardware for 3-source instructions. Since gen8, > when the half-float type was added, 3-source floating point

[Mesa-dev] [PATCH] i965: Be resilient in the face of GPU hangs

2019-02-16 Thread Chris Wilson
If we hang the GPU and end up banning our context, we will no longer be able to submit and abort with an error (exit(1) no less). As we submit minimal incremental batches that rely on the logical context state of previous batches, we can not rely on the kernel's recovery mechanism which tries to

[Mesa-dev] [PATCH v2 3/3] i965: Be resilient in the face of GPU hangs

2019-02-16 Thread Chris Wilson
If we hang the GPU and end up banning our context, we will no longer be able to submit and abort with an error (exit(1) no less). As we submit minimal incremental batches that rely on the logical context state of previous batches, we can not rely on the kernel's recovery mechanism which tries to

Re: [Mesa-dev] [PATCH v4 35/40] intel/compiler: validate conversions between 64-bit and 8-bit types

2019-02-16 Thread Jason Ekstrand
On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_eu_validate.c| 10 +- > src/intel/compiler/test_eu_validate.cpp | 46 + > 2 files changed, 55 insertions(+), 1 deletion(-) > > diff --git

Re: [Mesa-dev] [PATCH v4 20/40] intel/compiler: workaround for SIMD8 half-float MAD in gen8

2019-02-16 Thread Jason Ekstrand
On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > Empirical testing shows that gen8 has a bug where MAD instructions with > a half-float source starting at a non-zero offset fail to execute > properly. > > This scenario usually happened in SIMD8 executions, where we used to > pack

Re: [Mesa-dev] [PATCH v4 01/40] compiler/nir: add an is_conversion field to nir_op_info

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 11:51 AM Iago Toral Quiroga wrote: > This is set to True only for numeric conversion opcodes. > --- > src/compiler/nir/nir.h| 3 ++ > src/compiler/nir/nir_opcodes.py | 73 +-- >

Re: [Mesa-dev] [PATCH v4 14/40] intel/compiler: add new half-float register type for 3-src instructions

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 5:57 AM Iago Toral Quiroga wrote: > This is available since gen8. > > v2: restore previously existing assertion. > > v3: don't use separate tables for gen7 and gen8, just assert that we > don't use half-float before gen8 (Matt) > >

[Mesa-dev] [PATCH v2 1/3] i965: Assert the execobject handles match for this device

2019-02-16 Thread Chris Wilson
Object handles are local to the device fd, so double check we are not mixing together objects from multiple screens on execbuf submission. Cc: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

Re: [Mesa-dev] [PATCH v4 32/40] intel/compiler: skip MAD algebraic optimization for half-float or mixed mode

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 5:56 AM Iago Toral Quiroga wrote: > It is very likely that this optimzation is never useful and we'll probably > just end up removing it, so let's not bother adding more cases to it for > now. > --- > src/intel/compiler/brw_fs.cpp | 4 >

Re: [Mesa-dev] [PATCH v4 00/40] intel: VK_KHR_shader_float16_int8 implementation

2019-02-16 Thread Jason Ekstrand
I believe I've now reviewed everything except some of the validator patches and the is_partial_write() patch. The validator patches I'm hoping Matt or Curro can look at. For the is_partial_write() patch, I just need to convince myself that it doesn't make the compiler significantly more bogus

Re: [Mesa-dev] [PATCH v4 27/40] intel/compiler: generalize the combine constants pass

2019-02-16 Thread Jason Ekstrand
On Tue, Feb 12, 2019 at 5:57 AM Iago Toral Quiroga wrote: > At the very least we need it to handle HF too, since we are doing > constant propagation for MAD and LRP, which relies on this pass > to promote the immediates to GRF in the end, but ideally > we want it to support even more types so we

Re: [Mesa-dev] [PATCH 2/2] i965: Be resilient in the face of GPU hangs

2019-02-16 Thread Kenneth Graunke
On Thursday, February 14, 2019 4:05:00 AM PST Chris Wilson wrote: > If we hang the GPU and end up banning our context, we will no longer be > able to submit and abort with an error (exit(1) no less). As we submit > minimal incremental batches that rely on the logical context state of > previous

Re: [Mesa-dev] [PATCH v4 31/40] intel/compiler: remove inexact algebraic optimizations from the backend

2019-02-16 Thread Jason Ekstrand
Reviewed-by: Jason Ekstrand On Tue, Feb 12, 2019 at 5:57 AM Iago Toral Quiroga wrote: > NIR already has these and correctly considers exact/inexact qualification, > whereas the backend doesn't and can apply the optimizations where it > shouldn't. This happened to be the case in a handful of

Re: [Mesa-dev] [PATCH v4 34/40] intel/compiler: validate region restrictions for half-float conversions

2019-02-16 Thread Jason Ekstrand
On Tue, Feb 12, 2019 at 11:53 AM Iago Toral Quiroga wrote: > --- > src/intel/compiler/brw_eu_validate.c| 64 - > src/intel/compiler/test_eu_validate.cpp | 122 > 2 files changed, 185 insertions(+), 1 deletion(-) > > diff --git

[Mesa-dev] [Bug 109532] ir_variable has maximum access out of bounds -- but it's not out of bounds

2019-02-16 Thread bugzilla-daemon
https://bugs.freedesktop.org/show_bug.cgi?id=109532 --- Comment #32 from andrii simiklit --- (In reply to andrii simiklit from comment #31) > (In reply to Mark Janes from comment #30) > > (In reply to Mark Janes from comment #28) > > > > > >

Re: [Mesa-dev] radeonsi: NIR - Polaris triangle sprinkling running UH SOLVED - finally

2019-02-16 Thread Dieter Nützel
Am 16.02.2019 03:56, schrieb Timothy Arceri: On 13/2/19 8:28 am, Dieter Nützel wrote: Hello Marek, Timo, Nicolai, Timo SOLVED this long-standing NIR corruption on Polaris with his 'nir: rewrite varying component packing' commit. It was triggered with commit