Re: [Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v9)

Hi Dave, -Ursprüngliche Nachricht- Von: mesa-dev Im Auftrag von Dave Airlie Gesendet: Montag, 9. Juli 2018 23:15 An: mesa-dev@lists.freedesktop.org Betreff: [Mesa-dev] [PATCH] radv: using tls to store llvm related info and speed up compiles (v9) From: Dave Airlie This uses the common

Re: [Mesa-dev] [PATCH 6/7] ac: handle subgroup intrinsics

HI Daniel, Am 08.03.2018 um 18:10 schrieb Daniel Schürmann: --- src/amd/common/ac_nir_to_llvm.c | 66 +++-- 1 file changed, 37 insertions(+), 29 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 9b85069860..

Re: [Mesa-dev] [PATCH 3/7] ac: lower 64bit subgroup intrinsics

Hi Daniel, Am 08.03.2018 um 18:10 schrieb Daniel Schürmann: --- src/amd/common/ac_lower_subgroups.c | 50 ++--- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_lower_subgroups.c b/src/amd/common/ac_lower_subgroups.c index d078

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Avoid unnecessary transitions before fast clears

HI Jason, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Montag, 26. Februar 2018 03:33 An: mesa-dev@lists.freedesktop.org Cc: Jason Ekstrand Betreff: [Mesa-dev] [PATCH] anv/cmd_buffer: Avoid unnecessary tra

Re: [Mesa-dev] [PATCH] ac/nir: fix user sgpr allocations on gfx9

Hi Dave Am 19.01.2018 um 00:22 schrieb Dave Airlie: From: Dave Airlie The code to decide how to allocate sgprs didn't take into account the merged shaders on gfx9. This updates the code to count the correct number of requires sgprs, which means we should be able to enable push const inlining

Re: [Mesa-dev] [PATCH 3/8] spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory

Hi Jason, Am 07.12.2017 um 17:12 schrieb Jason Ekstrand: --- src/compiler/spirv/vtn_variables.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index cf44ed3..8ce19ff 100644 --- a

Re: [Mesa-dev] [PATCH 01/28] vulkan/wsi: use function ptr definitions from the spec.

Hi Jason, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Donnerstag, 16. November 2017 22:29 An: mesa-dev@lists.freedesktop.org Cc: Dave Airlie Betreff: [Mesa-dev] [PATCH 01/28] vulkan/wsi: use function ptr

Re: [Mesa-dev] [PATCH 1/4] intel/reg: Add helpers for 64-bit integer immediates

Hi Jason, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Freitag, 3. November 2017 05:53 An: mesa-dev@lists.freedesktop.org Cc: Jason Ekstrand Betreff: [Mesa-dev] [PATCH 1/4] intel/reg: Add helpers for 64-bi

Re: [Mesa-dev] [PATCH v2 2/3] glsl: check if induction var incremented before use in terminator

Out of curriosity what about decrement and other shenanigans? --Michael Am 21.09.2017 um 12:55 schrieb Timothy Arceri: do-while loops can increment the starting value before the condition is checked. e.g. do { ndx++; } while (ndx < 3); This commit changes the code to detect this a

Re: [Mesa-dev] [PATCH 6/7] i965/fs/nir: Don't stomp 64-bit values to D in get_nir_src

Hi Jason, given that 16bit types are already on the horizon a switch(nir_src_bit_size(src)) seems more future-proof --Michael Am 28.08.2017 um 16:51 schrieb Jason Ekstrand: --- src/intel/compiler/brw_fs_nir.cpp | 38 ++ 1 file changed, 26 insertions(

Re: [Mesa-dev] [PATCH] radeonsi: do not assert when reserving bindless slot 0

Hi Samuel, do you want to fully remove the assert or should this be something the kind of MAYBE_UNUSED unsigned res = util_idalloc_alloc(&sctx->bindless_used_slots); assert(res != 0); --Michael -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Au

Re: [Mesa-dev] [PATCH 2/2] intel/isl: Replace switch statements of doom with a macro

Hi Jason, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Donnerstag, 17. August 2017 23:57 An: mesa-dev@lists.freedesktop.org Cc: Jason Ekstrand Betreff: [Mesa-dev] [PATCH 2/2] intel/isl: Replace switch stat

Re: [Mesa-dev] [PATCH 1/5] i965: Enable non-CCS_E fast-clears on gen9+

Hi Jason On 15.06.2017 03:54, Jason Ekstrand wrote: > Sky Lake and above can fast-clear exactly the same set of formats as > older hardware. The only restriction is that you can't *texture* from > it unless the format supports CCS_E but you can fast-clear and render to > it just fine. All of th

Re: [Mesa-dev] [PATCH 1/2] mesa: create locked version of HashWalk

Him Tim, I hadnt had my morning coffee butdidnt you do it the other way around? It looks like, that "_mesa_HashWalk" ist he locked and "_mesa_HashWalkLocked" the unlocked version. Michael -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag

Re: [Mesa-dev] [PATCH 4/4] radv: Implement pipeline statistics queries.

Hi Bas, it seems like this junk + nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_store_ssbo); + store->src[0] = nir_src_for_ssa(available); + store->src[1] = nir_src_for_ssa(&dst_buf->dest.ssa); + store->src[2] = nir_src_for_ssa(nir_iadd(

Re: [Mesa-dev] [PATCH] radv/ac: enable loop unrolling. (v2)

Hi Dave, -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Dave Airlie Gesendet: Freitag, 24. Februar 2017 04:59 An: mesa-dev@lists.freedesktop.org Betreff: [Mesa-dev] [PATCH] radv/ac: enable loop unrolling. (v2) From: Dave Airlie Th

Re: [Mesa-dev] [PATCH] intel/aubinator: Use the correct length for MEDIA commands

Hi Jason, this would be the same as case 3. Is that intentional and if so would you combine the cases? --Michael -Ursprüngliche Nachricht- Von: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] Im Auftrag von Jason Ekstrand Gesendet: Dienstag, 22. November 2016 03:59 An: mesa-dev

Re: [Mesa-dev] [PATCH 10/18] anv/image: Memset all aux surfaces (not just HiZ) to 0

Hi Jason, the first word of the comment should be auxiliary? --Michael Am 28.10.2016 um 11:17 schrieb Jason Ekstrand: > Signed-off-by: Jason Ekstrand > --- > src/intel/vulkan/anv_image.c | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/src/intel/vulkan/anv_i

Re: [Mesa-dev] [PATCH] glsl: optimize list handling in opt_dead_code

Hi Jan, On 18.10.2016 00:07, Jan Ziak wrote: This patch replaces the ir_variable_refcount_entry's linked-list with an array-list. The array-list has local storage which does not require ANY additional allocations if the list has small number of elements. The size of this storage is configurabl

Re: [Mesa-dev] [PATCH 3/4] i965/blorp: Add a copy_miptrees helper

Hi Jason, On 09.09.2016 19:05, Jason Ekstrand wrote: --- src/mesa/drivers/dri/i965/brw_blorp.c | 71 +++ src/mesa/drivers/dri/i965/brw_blorp.h | 10 + 2 files changed, 81 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/driver

Re: [Mesa-dev] [PATCH 3/3] nir/spirv: Use fill_common_atomic_sources for image atomics

Hi Jason, Am 07.09.2016 um 00:17 schrieb Jason Ekstrand: > We had two almost identical copies of this code and they were both broken > but in different ways. The previous two commits fixed both of them. This > one just unifies them so that it's easier to handle in the future. > > Signed-off-by:

[Mesa-dev] [PATCH 3/3] gallium: Fix incorrect unreachable call

Signed-off-by: Michael Schellenberger Costa --- src/gallium/state_trackers/nine/nine_shader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/nine/nine_shader.c b/src/gallium/state_trackers/nine/nine_shader.c index bd373d7..4c58a6d 100644 --- a/src

[Mesa-dev] [PATCH] mesa/st: Standardize some asserts to use !"foo"

These are the final asserts in the tree that do not follow the pattern assert(!"foo"). To simplify spotting of (mostly) incorrect asserts via git grep "assert(\"" rewrite them into the standard form. Signed-off-by: Michael Schellenberger Costa --- src/mesa/state_tr

[Mesa-dev] [PATCH 1/3] anv: Fix incorrect unreachable call

Signed-off-by: Michael Schellenberger Costa --- src/intel/vulkan/anv_meta_blit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_meta_blit.c b/src/intel/vulkan/anv_meta_blit.c index d2e375a..6f73102 100644 --- a/src/intel/vulkan/anv_meta_blit.c +++ b/src

[Mesa-dev] [PATCH 2/3] glsl: Fix incorrect unreachable call

Signed-off-by: Michael Schellenberger Costa --- src/compiler/glsl/ir_print_visitor.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/ir_print_visitor.cpp b/src/compiler/glsl/ir_print_visitor.cpp index 0dd1c35..4cb8069 100644 --- a/src/compiler/glsl

[Mesa-dev] [PATCH] anv: Fix incorrect assert in anv_wsi_wayland.c

Signed-off-by: Michael Schellenberger Costa --- src/intel/vulkan/anv_wsi_wayland.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_wsi_wayland.c b/src/intel/vulkan/anv_wsi_wayland.c index a9e1617..d210e79 100644 --- a/src/intel/vulkan/anv_wsi_wayland.c

Re: [Mesa-dev] [PATCH v2] i965/vec4: make offset() operate in terms of channels instead of full registers

Hi Iago, given that the idea here was to unify vec4 and fs you might want to adopt the names/function types accordingly. In brw_ir_fs.h there is byte_offset that returns a fs_reg while you have void add_byte_offset. --Michael Am 23.08.2016 um 10:24 schrieb Iago Toral Quiroga: > This will make i

Re: [Mesa-dev] [PATCH 2/4] i965/vec4: make the offset() operate in terms of width and type

Hi Iago, Am 22.08.2016 um 11:53 schrieb Iago Toral Quiroga: > This will make it more consistent with the FS implementation of the same > helper and will provide more flexibility that will come in handy, for > example, when we add a SIMD lowering pass in the vec4 backend. > --- > src/mesa/drivers/

Re: [Mesa-dev] [PATCH v3 12/34] i965/miptree: Add a helper for getting the aux isl_surf from a miptree

Hi Jason, Am 30.06.2016 um 01:22 schrieb Jason Ekstrand: > v2: Switch on the usage when filling out formats > > Reviewed-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 119 > ++ > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++ > 2

Re: [Mesa-dev] [PATCH 1/6] radeonsi: extract IB and bo list saving into separate functions

Hi Nicolai Am 22.06.2016 um 11:40 schrieb Nicolai Hähnle: > From: Nicolai Hähnle > > --- > src/gallium/drivers/radeon/r600_pipe_common.c | 53 > +++ > src/gallium/drivers/radeon/r600_pipe_common.h | 12 ++ > src/gallium/drivers/radeonsi/si_debug.c | 39 +++

Re: [Mesa-dev] [PATCH 3/5] anv/descriptor_set: Ensure that bindings are always in increasing order

Hi Jason, Am 06/06/2016 um 20:26 schrieb Jason Ekstrand: > Since applications are allowed to specify some set of bindings which need > not be dense they also need not be in order. That sentence reads strange. "Need not be" sounds like must not. Dont you mean "Do not need to be"? --Michael For

Re: [Mesa-dev] [PATCH 4/5] anv/pipeline: Store the (set, binding, index) tripple in the bind map

Hi Jason Am 06/06/2016 um 20:26 schrieb Jason Ekstrand: > This way the the bind map (which we're caching) is mostly independent of double the here > the pipeline layout. The only coupling remaining is that we pull the array > size of a binding out of the layout. However, that size is also specif

Re: [Mesa-dev] [PATCH v2] i965: Fix point size with tessellation/geometry shaders in GLES.

Hi Kenneth, Am 03.06.2016 um 10:08 schrieb Kenneth Graunke: > Our previous code worked for desktop GL, and ES without geometry or > tessellation shaders. But those features require fancier point size > handling. Fortunately, we can use one rule for all APIs. > > Fixes a number of dEQP tests wit

Re: [Mesa-dev] [PATCH 2/4] anv/apply_dynamic_offsets: Use rewrite_src instead of a regular assignment

Hi Jason, Am 19.05.2016 um 06:42 schrieb Jason Ekstrand: > Originally we removed the instruction, changed the source, and then > re-inserted it. This works, but nir_instr_rewrite_src is a bit more > obviously correct. > --- > src/intel/vulkan/anv_nir_apply_dynamic_offsets.c | 6 +++--- > 1 file

Re: [Mesa-dev] [PATCH v3] glsl/linker: dvec3/dvec4 consume twice input vertex attributes

Hi Juan, Am 18.05.2016 um 13:19 schrieb Juan A. Suarez Romero: > From the GL 4.5 core spec, section 11.1.1 (Vertex Attributes): > > "A program with more than the value of MAX_VERTEX_ATTRIBS > active attribute variables may fail to link, unless > device-dependent optimizations are able to make the

Re: [Mesa-dev] [PATCH 01/13] vbo: Declare the index range invalid for DrawIndirect

Hi Jason, Am 19.05.2016 um 09:20 schrieb Jason Ekstrand: > Right now, we're just setting the range to [0, MAX_UINT32] which, while > correct isn't helpful. With DrawIndirect, you can't really know what the > actual range is so we may as well flag it as being an invalid range. This > is what we d

Re: [Mesa-dev] [PATCH 07/12] nir: Don't use ffma in nir_lower_wpos_ytransform().

Hi Kenneth, Am 19.05.2016 um 00:00 schrieb Kenneth Graunke: > ffma is an explicitly fused multiply add with higher precision. > The optimizer will take care of promoting mul/add to fma when > it's beneficial to do so. > > This fixes failures on Gen4-5 when using this pass, as those platforms > do

Re: [Mesa-dev] [PATCH v2 4/4] anv/pipeline: Bounds-check resource indices when robuts_buffer_access is enabled

Hi Jason, Am 19.05.2016 um 09:22 schrieb Jason Ekstrand: > --- > src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 52 > > 1 file changed, 35 insertions(+), 17 deletions(-) > > diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c > b/src/intel/vulkan/anv_nir_

Re: [Mesa-dev] [PATCH 1/2] i965: Reduce the SIMD8 GS push constant threshold from 32 to 24.

Hi Kenneth, can you update the comment too? Michael Am 10.05.2016 um 09:46 schrieb Kenneth Graunke: > Three Shadow of Mordor geometry shaders increase by a single > instruction, but the number of spills/fills in Orbital Explorer > is reduced from 194:1279 -> 82:454. No other programs are affect

Re: [Mesa-dev] [PATCHv2 10/23] i965/fs: Stop using the LOAD_PAYLOAD instruction in lower_simd_width.

Hi Curro, Am 04.05.2016 um 06:26 schrieb Francisco Jerez: > Instead of using the LOAD_PAYLOAD instruction (emitted through the > emit_transpose() helper that is no longer useful and this commit > removes) which had to be marked force_writemask_all in some cases, > emit a series of moves to apply p

Re: [Mesa-dev] [PATCH 02/18] anv: Add a new block-based batch emit macro

Hi Jason, stupid optional nitpick , but could you go for anv_batch_emit_block? Normally abbreviations below 3 characters aren't really worth it. Michael Am 19/04/2016 um 02:10 schrieb Jason Ekstrand: > This new macro uses a for loop to create an actual code block in which to > place the macro se

Re: [Mesa-dev] [PATCH 2/4] radeonsi: Set range metadata on calls to llvm.SI.tid

Hi Tom, Am 19.04.2016 um 19:52 schrieb Tom Stellard: > The range metadata tells LLVM the range of expected values for this intrinsic, > so it can do some additional optimizations on the result. > --- > src/gallium/drivers/radeonsi/si_shader.c | 29 ++--- > 1 file changed,

Re: [Mesa-dev] [PATCH 3/4] radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid v2

Hi Tom Am 19.04.2016 um 19:52 schrieb Tom Stellard: > We're trying to move to more of the new style intrinsics with include > the correct target name, and map directly to ISA instructions. > > v2: > - Only do this with LLVM 3.8 and newer. > --- > src/gallium/drivers/radeonsi/si_shader.c | 17 ++

Re: [Mesa-dev] [PATCH 1/6] i965/vec4: Move can_do_writemask to vec4_instruction

Hi Jason, Am 06.04.2016 um 06:11 schrieb Jason Ekstrand: > --- > src/mesa/drivers/dri/i965/brw_ir_vec4.h| 1 + > src/mesa/drivers/dri/i965/brw_vec4.cpp | 28 +++ > .../dri/i965/brw_vec4_dead_code_eliminate.cpp | 31 > +- > 3 files

Re: [Mesa-dev] [PATCH 4/6] i965/vec4: Handle MOV_INDIRECT in pack_uniform_registers

Hi Jason, Am 06.04.2016 um 06:11 schrieb Jason Ekstrand: > --- > src/mesa/drivers/dri/i965/brw_vec4.cpp | 18 ++ > 1 file changed, 18 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp > b/src/mesa/drivers/dri/i965/brw_vec4.cpp > index e2aa109..6433fc5 100644 >

Re: [Mesa-dev] [PATCH 01/41] glapi: clean imports in python files

Hi, minor nitpicks wrt ordering below Am 01.04.2016 um 02:04 schrieb Dylan Baker: > Completely clean the imports: > - Split so that one module is imported per line > - Remove unused imports > - Group stdlib imports, then 3rd party modules, and finally local > modules > - sort alphabetically wit

Re: [Mesa-dev] [PATCH 01/12] nvc0: allocate an area for compute user constbufs

Hi, Am 06/02/2016 um 23:38 schrieb Samuel Pitoiset: > For compute shaders, we might need to upload uniforms. > > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 14 +++--- > src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 12 +

Re: [Mesa-dev] [PATCH 2/4] st/mesa: unify get_variant functions for TCS, TES, GS

Hi Am 30/01/2016 um 16:50 schrieb Marek Olšák: > From: Marek Olšák > > --- > src/mesa/state_tracker/st_atom_shader.c | 18 +--- > src/mesa/state_tracker/st_program.c | 164 > +--- > src/mesa/state_tracker/st_program.h | 17 +--- > 3 files changed, 28 inser

Re: [Mesa-dev] [PATCH 2/2] i965: Implement nir_op_fquantize2f16

Hi Jason Am 13/01/2016 um 00:35 schrieb Jason Ekstrand: > --- > src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 + > src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 10 ++ > 2 files changed, 23 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp > b/src/mesa

Re: [Mesa-dev] [PATCH 1/9] st/glsl_to_tgsi: store if dst is double in array

Am 19/12/2015 um 05:43 schrieb Dave Airlie: > From: Dave Airlie > > This is just a precursor patch to a fix for doubles with > tessellation that I've written. > > We need to descend into output arrays in that case and > mark dst's as double. > > Signed-off-by: Dave Airlie > --- > src/mesa/s

Re: [Mesa-dev] [PATCH 05/15] i965/fs: Stop relying on param_size in assign_constant_locations

Hi, Am 10.12.2015 um 05:23 schrieb Jason Ekstrand: > Now that we have MOV_INDIRECT opcodes, we have all of the size information > we need directly in the opcode. With a little restructuring of the > algorithm used in assign_constant_locations we don't need param_size > anymore. The big thing to

Re: [Mesa-dev] [PATCH 04/53] r600: move to using hw stages array for hw stage atoms

Hi, Am 30.11.2015 um 07:20 schrieb Dave Airlie: > From: Dave Airlie > > This moves to using an array of hw stages for the atoms. > > Signed-off-by: Dave Airlie > --- > src/gallium/drivers/r600/evergreen_state.c | 8 +++- > src/gallium/drivers/r600/r600_hw_context.c | 8 > s

Re: [Mesa-dev] [PATCH 03/17] mesa: Move gl_frag_depth_layout from mtypes.h to shader_enums.h

Hi, as this conflicts directly with Robs patch http://lists.freedesktop.org/archives/mesa-dev/2015-October/096670.html you might want to update it Michael Am 09.10.2015 um 02:22 schrieb Jason Ekstrand: > --- src/glsl/shader_enums.h | 17 + > src/mesa/main/mtypes.h | 18 -

Re: [Mesa-dev] [PATCH] mesa: Correctly handle GL_BGRA_EXT in ES3 format_and_type checks

Hi, Am 08.10.2015 um 00:58 schrieb Jason Ekstrand: > The EXT_texture_format_BGRA extension (which mesa supports > unconditionally) adds a new format and internal format called > GL_BGRA_EXT. Previously, this was not really handled at all in > _mesa_ex3_error_check_format_and_type. When the

Re: [Mesa-dev] [PATCH] i965/miptree: Rename intel_miptree_map::mt -> ::linear_mt (v2)

Hi, Am 25/09/2015 um 23:24 schrieb Chad Versace: > Because that's what it is. It's an untiled, *linear* miptree. > > v2: - Add space after /*. - Use one comment per function argument. > --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 > ++- > src/mesa/drivers/dri/i9

Re: [Mesa-dev] [PATCH] nir: Fix output variable names

Hi, didnt Jason just send a similar patch to the list? [Mesa-dev] [PATCH] nir/lower_outputs_to_temporaries: Reparent the output name Regards Michael Am 11/09/2015 um 09:24 schrieb Eduardo Lima Mitev: > Commit 1dbe4af9c9e318525fc082b542b93fb7f1e5efba > "nir: Add a pass to lower outputs to tempor

Re: [Mesa-dev] [PATCH 04/11] nir: Add a function for rewriting instruction destinations

Hi, Am 10/09/2015 um 02:50 schrieb Jason Ekstrand: > --- > src/glsl/nir/nir.c | 24 > src/glsl/nir/nir.h | 2 ++ > 2 files changed, 26 insertions(+) > > diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c > index e173b21..0090b08 100644 > --- a/src/glsl/nir/nir.c > +++

Re: [Mesa-dev] [PATCH 3/5] nir: Add new GS intrinsics that maintain a count of emitted vertices.

Am 03.09.2015 um 10:48 schrieb Kenneth Graunke: > This patch also introduces a lowering pass to convert the simple GS > intrinsics to the new ones. See the comments above that for the > rationale behind the new intrinsics. > > This should be useful for i965; it's a generic enough mechanism that I

Re: [Mesa-dev] [PATCH 07/20] i965/fs: Import image memory offset calculation code.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, Am 21.07.2015 um 18:38 schrieb Francisco Jerez: > Define a function to calculate the memory address of the image > location given by a vector of coordinates. This is required in > cases where we need to fall back to untyped surface access, which

Re: [Mesa-dev] [PATCH 3/7] tgsi: add support for geometry shader streams.

Hi, Am 27/05/2015 um 09:45 schrieb Dave Airlie: > This adds support to retrieve the primitive counts > for each stream, along with the offset for each > primitive into the output array. > > It also adds support for parsing the stream argument > to the emit and end instructions. > > Signed-off-by

Re: [Mesa-dev] [PATCH 3/7] tgsi: add support for geometry shader streams.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, Am 27.05.2015 um 09:45 schrieb Dave Airlie: > This adds support to retrieve the primitive counts for each stream, > along with the offset for each primitive into the output array. > > It also adds support for parsing the stream argument to the em

Re: [Mesa-dev] [PATCH 2/4] radeon: Make use of _mesa_get_viewport_xform.

-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, could you use the same ordering as in the 1965 patch? scale[0] scale[1] scale[2] translate[0] translate[1] translate[2] This simplifies reading and comparing a lot. Best wishes Michael -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.22 (GNU/L