Re: [Mesa-dev] [Intel-gfx] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

2018-05-11 Thread Michel Thierry
On 5/11/2018 5:43 AM, Mika Kuoppala wrote: Chris Wilson writes: Quoting Mika Kuoppala (2018-05-11 10:56:49) Michel Thierry writes: Factor in clear values wherever required while updating destination min/max. References: HSDES#160184 Signed-off-by: Michel Thierry Cc: mesa-dev

[Mesa-dev] [PATCH] drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk

2018-05-10 Thread Michel Thierry
Factor in clear values wherever required while updating destination min/max. References: HSDES#160184 Signed-off-by: Michel Thierry Cc: mesa-dev@lists.freedesktop.org Cc: Mika Kuoppala Cc: Oscar Mateo --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915

Re: [Mesa-dev] [PATCH] intel: Future-proof ring names for aubinator_error_decode

2018-01-18 Thread Michel Thierry
state to use the new naming scheme. This of course means we need to teach aubinator_error_decode how to map both sets of ring names onto its register maps. Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: Lionel Landwerlin Cc: Kenneth Graunke

[Mesa-dev] [PATCH v5 10/18] drm/i915: Add engine reset count in get-reset-stats ioctl

2017-03-24 Thread Michel Thierry
it is deemed useful, it can be extended to report each engine separately. v2: s/engine_reset/reset_engine/, use union in uapi to not break compatibility. Cc: Chris Wilson Cc: Mika Kuoppala Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915

[Mesa-dev] [PATCH 10/10] drm/i915: Add engine reset count in get-reset-stats ioctl

2017-01-12 Thread Michel Thierry
it is deemed useful, it can be extended to report each engine separately. v2: s/engine_reset/reset_engine/. Cc: Chris Wilson Cc: Mika Kuoppala Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 14 +++--- include/uapi/drm

[Mesa-dev] [RFC 9/9] drm/i915: Add engine reset count in get-reset-stats ioctl

2016-12-16 Thread Michel Thierry
it is deemed useful, it can be extended to report each engine separately. Cc: Chris Wilson Cc: Mika Kuoppala Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/i915_gem_context.c | 14 +++--- include/uapi/drm/i915_drm.h | 3 ++- 2 files

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-12-04 Thread Michel Thierry
On 11/18/2015 10:53 PM, Kristian Høgsberg wrote: On Wed, Oct 14, 2015 at 5:11 AM, Michel Thierry wrote: On 10/14/2015 8:19 AM, Daniel Vetter wrote: On Tue, Oct 13, 2015 at 02:51:36PM -0700, Kristian Høgsberg wrote: On Tue, Oct 13, 2015 at 7:55 AM, Michel Thierry wrote: On 10/13/2015 3

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-10-14 Thread Michel Thierry
On 10/14/2015 8:19 AM, Daniel Vetter wrote: On Tue, Oct 13, 2015 at 02:51:36PM -0700, Kristian Høgsberg wrote: On Tue, Oct 13, 2015 at 7:55 AM, Michel Thierry wrote: On 10/13/2015 3:13 PM, Emil Velikov wrote: On 13 October 2015 at 13:16, Michel Thierry wrote: On 10/6/2015 2:12 PM, Michel

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-10-13 Thread Michel Thierry
On 10/13/2015 3:13 PM, Emil Velikov wrote: On 13 October 2015 at 13:16, Michel Thierry wrote: On 10/6/2015 2:12 PM, Michel Thierry wrote: On 10/5/2015 7:06 PM, Kristian Høgsberg wrote: On Mon, Oct 5, 2015 at 7:03 AM, Michel Thierry wrote: On 9/14/2015 2:54 PM, Michał Winiarski wrote

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-10-13 Thread Michel Thierry
On 10/6/2015 2:12 PM, Michel Thierry wrote: On 10/5/2015 7:06 PM, Kristian Høgsberg wrote: On Mon, Oct 5, 2015 at 7:03 AM, Michel Thierry wrote: On 9/14/2015 2:54 PM, Michał Winiarski wrote: On Thu, Sep 03, 2015 at 03:23:58PM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-10-06 Thread Michel Thierry
On 10/5/2015 7:06 PM, Kristian Høgsberg wrote: On Mon, Oct 5, 2015 at 7:03 AM, Michel Thierry wrote: On 9/14/2015 2:54 PM, Michał Winiarski wrote: On Thu, Sep 03, 2015 at 03:23:58PM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be

[Mesa-dev] [RFC v4] i965/gen8+: bo in state base address must be in 32-bit address range

2015-10-05 Thread Michel Thierry
, libdrm requires to set the support flag before calling emit_reloc. References: http://lists.freedesktop.org/archives/dri-devel/2015-September/089757.html Cc: Ben Widawsky Cc: Chris Wilson Signed-off-by: Michel Thierry --- configure.ac | 2 +- src/mesa

Re: [Mesa-dev] [PATCH v4 1/2] intel: 48b ppgtt support (EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag)

2015-10-05 Thread Michel Thierry
On 9/14/2015 2:54 PM, Michał Winiarski wrote: On Thu, Sep 03, 2015 at 03:23:58PM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v3] i965/gen8+: bo in state base address must be in 32-bit address range

2015-08-10 Thread Michel Thierry
Hi, Thanks for the comments, On 8/7/2015 11:46 PM, Kristian Høgsberg wrote: On Fri, Aug 7, 2015 at 2:45 AM, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat

[Mesa-dev] [PATCH libdrm v3 0/2] 48-bit virtual address support in i915

2015-08-07 Thread Michel Thierry
erged, I'll make a new libdrm release and address the mesa build dependency. Michel Thierry (2): intel: Add EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag intel: add new function name to symbol-check test include/drm/i915_drm.h| 3 ++- intel/intel-symbol-check | 1 + intel/intel_bufmgr.c

[Mesa-dev] [PATCH libdrm v3 2/2] intel: add new function name to symbol-check test

2015-08-07 Thread Michel Thierry
Signed-off-by: Michel Thierry --- intel/intel-symbol-check | 1 + 1 file changed, 1 insertion(+) diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check index c555e6d..6f8450b 100755 --- a/intel/intel-symbol-check +++ b/intel/intel-symbol-check @@ -18,6 +18,7 @@ drm_intel_bo_busy

Re: [Mesa-dev] [Intel-gfx] [PATCH libdrm v3 1/2] intel: Add EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag

2015-08-07 Thread Michel Thierry
On 8/7/2015 11:56 AM, Michał Winiarski wrote: On Fri, Aug 07, 2015 at 10:45:21AM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. In specific, any resource used with flat/heapless (0x

[Mesa-dev] [PATCH mesa v3] i965/gen8+: bo in state base address must be in 32-bit address range

2015-08-07 Thread Michel Thierry
/2015-July/072612.html Cc: Ben Widawsky Cc: Chris Wilson Signed-off-by: Michel Thierry --- configure.ac | 2 +- src/mesa/drivers/dri/i965/gen8_misc_state.c | 19 +++ src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 src

[Mesa-dev] [PATCH libdrm v3 1/2] intel: Add EXEC_OBJECT_SUPPORTS_48B_ADDRESS flag

2015-08-07 Thread Michel Thierry
internal, no-one needs to use them directly. References: http://lists.freedesktop.org/archives/intel-gfx/2015-July/072612.html Cc: Ben Widawsky Cc: Dave Gordon Signed-off-by: Michel Thierry --- include/drm/i915_drm.h| 3 ++- intel/intel_bufmgr.c | 16 ++ intel

Re: [Mesa-dev] [Intel-gfx] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range

2015-07-02 Thread Michel Thierry
On 7/2/2015 8:21 AM, Chris Wilson wrote: On Wed, Jul 01, 2015 at 04:28:10PM +0100, Michel Thierry wrote: Gen8+ supports 48-bit virtual addresses, but some objects must always be allocated inside the 32-bit address range. OUT_BATCH(0); OUT_BATCH(mocs_wb << 16); /* Surface

[Mesa-dev] [PATCH mesa v2] i965/gen8+: bo in state base address must be in 32-bit address range

2015-07-01 Thread Michel Thierry
: s/48baddress/48b_address/, Only use in OUT_RELOC64 cases, OUT_RELOC implies a 32-bit address offset is needed (Ben) Cc: Ben Widawsky Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- configure.ac | 2 +- src/mesa/drivers/dri/i965

Re: [Mesa-dev] [PATCH mesa] i965/gen8+: bo in state base address must be in 32-bit address range

2015-06-25 Thread Michel Thierry
On 6/24/2015 4:51 AM, Ben Widawsky wrote: Hi. Feel free to Cc me on patches of this nature. I am far behind on mesa-dev, and no longer read intel-gfx. I'm probably one of the sensible people to look at this... On Tue, Jun 23, 2015 at 01:21:27PM +0100, Michel Thierry wrote: Gen8+ suppor

[Mesa-dev] [PATCH mesa] i965/gen8+: bo in state base address must be in 32-bit address range

2015-06-23 Thread Michel Thierry
State Offset and Instruction State Offset are limited to 32-bits. Set provided bo flag when the 4GB limit is not necessary, to be able to use the full address space. Cc: mesa-dev@lists.freedesktop.org Signed-off-by: Michel Thierry --- src/mesa/drivers/dri/i965/gen8_misc_state.c | 6 +++--- src