From: Kenneth Graunke
Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.
By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.
We use gene
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 155
"Anti-aliasing Enable" to "Anti-Aliasing Enable".
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/genxml/
Reviewed-by: Rafael Antognolli
On Wed, May 10, 2017 at 11:47:26AM -0700, Kenneth Graunke wrote:
> Modern GL specifications say that the point size should be 1.0 when
> gl_PointSize is unwritten and the last enabled stage is a geometry
> or tessellation shader. If it's a vertex
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:23AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml
This looks weird since it is the only value in this instruction which
the name doesn't look like a macro (with all caps). But it's not the
first case in all the xml's, so it's probably fine:
Reviewed-by: Rafael Antognolli
>
>
>
> --
> 2.9.
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:22AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/intel/genxml/gen10.xml b/src/inte
Indeed the other two commits are related to the no_error path, but I
think at least this one should be applied. So it is:
Reviewed-by: Rafael Antognolli
On Wed, Jun 14, 2017 at 07:33:12PM +0300, Plamena Manolova wrote:
> In blit_framebuffer we're already doing a NULL
> pointer check
Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_cc.c| 174 --
src/mesa/drivers/dri/i965/brw_state.h | 1
This is a bitmask, so it can't be a boolean. Also rename it so it matches
gen6+.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 182
Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen5.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 65479d2..4651
code that handles it.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 2 +-
4 files changed, 4 insertions(
ction.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 2 -
src/mesa/drivers/dri/i965/gen6_gs_state.c | 56 ---
src/mesa/drivers/dri/i965/genX_state_upload.c | 17 +++-
4 files ch
apply
to lower gens.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index
These fields are set by brw_clip_unit, so we need them when converting to
genxml.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen45.xml | 1 +
src/intel/genxml/gen5.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index
Just because it's not set doesn't mean that it doesn't exist. And since the
field is there on newer gens, having it on gen5 simplifies the code when
porting gen5 and lower.
Also add missing value to API Mode on CLIP_STATE on gen4.
Signed-off-by: Rafael Antognolli
---
src/intel/
On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register
Count, but we can make the code that handles this on multiple gens simpler if
we add an index 0 to it too.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 4 ++--
src/intel/genxml/gen45
In newer gens, this field has a prefix and the non-I-745 mode is called
"Alternate", instead of simply "Alt".
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen6.xm
The code doesn't get exactly a lot simpler but at least it is in a
single place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_clip_state.c| 147 ---
src
"Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's
called on newer gens.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml
Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_gs_state.c | 101 --
src/mesa/drivers/dri/i965
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_cc.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/drivers/dr
From: Kenneth Graunke
Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.
By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.
We use gene
It's a very simple conversion, and it allows us to delete brw_cc.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_cc.c| 62 ---
src/mesa/drivers/dri/i965/genX_state_upload.c
The code doesn't get exactly a lot simpler but at least it is in a single
place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri
On Sat, Jun 17, 2017 at 10:38:26AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:24 PM PDT Rafael Antognolli wrote:
> > gen6+ uses _mesa_base_format_has_channel() to check for the alpha
> > channel, while gen4-5 use ctx->DrawBuffer->Visua
On Sat, Jun 17, 2017 at 10:32:44AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:23 PM PDT Rafael Antognolli wrote:
> > Add a helper function to reuse code that fills blend entry related
> > state, and make genX(upload_blend_state) use it. This function can later
On Sat, Jun 17, 2017 at 11:31:51AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:25 PM PDT Rafael Antognolli wrote:
> > Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
> > color calc struct, and then manually update the rest.
> >
>
On Mon, Jun 19, 2017 at 09:46:30AM -0700, Kristian Høgsberg wrote:
> On Fri, Jun 16, 2017 at 4:31 PM, Rafael Antognolli
> wrote:
> > The code doesn't get exactly a lot simpler but at least it is in a single
> > place, and we delete more than we add.
>
> Another good
This makes the code more consistent accross generations.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_cc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa
It's a very simple conversion, and it allows us to delete brw_cc.c.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_cc.c| 62 ---
src/mesa/drivers/dri
Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_gs_state.c | 101 --
src/mesa/drivers/dri/i965
apply
to lower gens.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri
These were originally used to submit state changes using manual packing
of instructions, but we are now using genxml for that. So it should be
safe to just remove them.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_defines.h | 729 +---
1 file
e use generation-defined typedef to handle the polymorphism.
Reviewed-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 113 +++---
1 file changed, 65 insertions(+), 48 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/dr
ction.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 2 -
src/mesa/drivers/dri/i965/gen6_gs_state.c | 56 ---
src/mesa/drivers/dri/i965/genX_state_upl
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_cc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/d
ructs. Now we're down to
just GENXML and some manual packing. (Khristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/brw_structs.h | 121
Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.
v2:
- Always check for depth_irb (Ken)
- Always set Backface Stencil Ref (Ken)
- Always set alpha reference value (Ken)
Signed-off-by: Rafael Antognolli
The code doesn't get exactly a lot simpler but at least it is in a
single place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_clip_state.c| 147 ---
src
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:20AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 69
> +++---
> 1 file changed, 65 insertions(+), 4 deletions(-)
>
> d
There are a few fields missing but they don't seem to be used anyway, so:
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:21AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 115
> +
ot;/>
> + type="uint"/>
> + type="bool"/>
> + type="bool"/>
> + type="bool"/>
> + type="bool"/>
> +
Bit 14 and 1 changed name. Bits 8-6, and 4 seem to have been removed. And I
believe the resp
On Thu, Nov 09, 2017 at 12:59:12AM -0800, Jordan Justen wrote:
> Reviewed-by: Jordan Justen
It's also
Tested-by: Rafael Antognolli
> On 2017-11-08 10:56:00, Kenneth Graunke wrote:
> > Similar to what we did for pixel shader threads - see gen_device_info.c.
> >
> &
On Thu, Nov 09, 2017 at 01:50:29PM -0800, Kenneth Graunke wrote:
> On Thursday, November 9, 2017 11:22:34 AM PST Rafael Antognolli wrote:
> > On Thu, Nov 09, 2017 at 12:59:12AM -0800, Jordan Justen wrote:
> > > Reviewed-by: Jordan Justen
> >
> > It's also
&g
On Fri, Nov 10, 2017 at 10:46:03AM +, Julien Isorce wrote:
> Thx for the suggestions.
>
> Anyone familiar with _mesa_get_format_block_size and _mesa_get_format_bytes
> wants to review this patch ?
>
> On 9 November 2017 at 17:10, Eric Engestrom wrote:
>
> On Thursday, 2017-11-09 17:03:
Since it's anv, I would like to hear from Jason or Nanley too. But it
does seem to implement the workaround correctly, like we do in i965, so
you have my
Reviewed-by: Rafael Antognolli
On Thu, Nov 09, 2017 at 11:14:42AM -0800, Anuj Phogat wrote:
> We already have this workaround i
On Thu, Nov 09, 2017 at 11:14:43AM -0800, Anuj Phogat wrote:
> On CNL this bit has been moved to CACHE_MODE_SS register.
> We already have this enabled in OpenGL driver.
> See Mesa commit 6c681b4cc1
>
> Signed-off-by: Anuj Phogat
> Cc: Nanley Chery
> Cc: Rafael Antognoll
It seems I missed that one when reviewing before, thank you.
Reviewed-by: Rafael Antognolli
On Fri, Nov 10, 2017 at 01:39:22PM -0800, Jason Ekstrand wrote:
> Found by inspection
>
> Fixes: d3d0fe4572f62474b86ef3a68405046c68b54062
> Cc: Anuj Phogat
> ---
> src/mes
Reviewed-by: Rafael Antognolli
On Tue, Nov 14, 2017 at 03:24:36PM -0800, Kenneth Graunke wrote:
> ...and provide a better citation for the existing one.
>
> v2:
> - Apply the workaround to Gen8 too, as intended (caught by Topi).
> - Restructure to add bits instead of an extra fl
Xorg (and possibly other things) depend on this variable to find the
path to DRI drivers.
Signed-off-by: Rafael Antognolli
Cc: Dylan Baker
---
src/mesa/drivers/dri/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri
On Wed, Apr 26, 2017 at 11:15:45PM -0700, Kenneth Graunke wrote:
> On Monday, April 24, 2017 3:19:21 PM PDT Rafael Antognolli wrote:
> [snip]
> > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> > b/src/mesa/drivers/dri/i965/genX_state_upload.c
> > index
Fill out "Attribute Active Component Format" possible values.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen9.xml | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9
g in a new genX_state_upload.c file.
i965: Get real per-gen atom lists
i965: Port Gen6+ DEPTH_STENCIL state to genxml.
Louis-Francis Ratté-Boulianne (1):
genxml: Fill out Gen4, Gen45 and Gen5 XML
Rafael Antognolli (33):
genxml: Rename clip enable property.
genxml: Update xml for 3DSTATE_SF
Name the options to "Pixel Location":
- PIXLOC_CENTER -> CENTER
- PIXLOC_UL_CORNER -> UL_CORNER
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/blorp/blorp_genX_exec.h | 4 +---
src/intel/genxml/gen6.xml | 4 ++--
src/intel/genxml/gen7
Emit 3DSTATE_TE on Gen7+ using brw_batch_emit helper.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen7_te_state.c | 67
From: Kenneth Graunke
Both GS and SOL have these fields. Some were ReorderEnable = true,
some were ReorderMode = REORDER_TRAILING, and some were just TRAILING.
Signed-off-by: Kenneth Graunke
Reviewed-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml| 5 -
src/intel/genxml/gen7
From: Kenneth Graunke
v3:
- Drop aub parameter (Ken)
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 15 ++-
src/mesa/drivers/dri/i965/genX_state_upload.c | 109 +++-
2 files changed, 119 insertions(+), 5 deletions(-)
create mode 100644 s
There are two variants:
- Clip Enable
- CLIP Enable (on gen6)
Rename everything to Clip Enable.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/intel/genxml
Use an alias, so we can set the same value as the #define's.
v3:
- Call it "SO Buffer MOCS" to follow the most common naming scheme.
- Add alias for gen7 and gen75 too (Ken).
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen7.xml | 1 +
src/intel/genxml/gen75
This makes genxml create the right struct types, and generate the right
batch commands.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen6.xml | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/genxml/gen6.xml b/src/intel
Ported in this patch:
- 3DSTATE_DS
- 3DSTATE_GS
- 3DSTATE_HS
- 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL
v3:
- Remove NEW_TRANSFORM blocks (Ken)
- Bring back some comments and workaround for Ivybridge (Ken)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965
- Normalize "Anti-Aliasing Enable"
- Add "Multisample Rasterization Mode" constants
- Rename "Use Point Width on Vertex" to "Vertex"
- Rename "Use Point Width from State" to "State"
Signed-off-by: Rafael Antognolli
Revie
)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 14 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 221 +---
src/mesa/drivers/dri/i965/gen7_wm_state.c
macro (Ken)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 4 +-
src/mesa/drivers/dri/i965/brw_state.h | 5 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 33 +---
src/mesa/drivers/dri/i965/gen6_vs_state.c | 70 +--
src/mesa/drivers
From: Kenneth Graunke
Make atoms initalization compile conditionally based on the target
platform.
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +-
src/mesa/drivers/dri/i965/brw_state_upload.c | 385 +---
src/mesa/drivers/dri/i965/genX_state_upload.c | 340 +++
This function now lives inside genX_state_upload.c.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 8 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 265
)
- Use macros for MOCS values.
- Do not use #ifndef NDEBUG on code that is actually used (Ken)
v3:
- Style and code clenup (Ken)
- Keep some of the common code inside brw_draw_upload.c (Ken)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 454
Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use render_bo helper to setup brw_address (Kristian)
v3:
- Bring back some comments for gen6 and remove _NEW_TRANSFORM blocks
from gen7+.
Signed-off-by: Rafael Antognolli
Reviewed-by
Emit 3DSTATE_SBE on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use ACTIVE_COMPONENT_XYZW from gen9.xml.
v3:
- Style fixes (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 2 +-
src
Emit sf state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
v3:
- Reorganize code and reduce #if/#endif's (Ken)
- Style fixes (Ken)
- Always set AALINEDISTANCE_TRUE (Ken)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h
Emit 3DSTATE_PS on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Use render_bo helper to setup brw_address (Kristian)
v3:
- Style fixes and code cleanup (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965
From: Kenneth Graunke
This emits 3DSTATE_WM_DEPTH_STENCIL on Gen8+ or DEPTH_STENCIL_STATE
(and the relevant pointer packets) on Gen6-7.5 from a single function.
v3:
- Watch for BRW_NEW_BATCH too on gen8+ (Ken)
Signed-off-by: Kenneth Graunke
Signed-off-by: Rafael Antognolli
Reviewed-by
Rename that field name on genxml for:
- 3DSTATE_GS - gen6+
- 3DSTATE_DS - gen7+
- 3DSTATE_HS - gen7+
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/genxml/gen6.xml| 2 +-
src/intel/genxml/gen7.xml| 6 +++---
src/intel/genxml/gen75.xml
Emit 3DSTATE_PS_EXTRA on Gen8+ using brw_batch_emit helper, that uses
pack structs from genxml.
v3:
- Style fixes and moving code around to be cleaner (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa
-by: Rafael Antognolli
Acked-by: Reviewed-by: Kenneth Graunke
---
src/intel/Makefile.sources | 1 +-
src/intel/compiler/brw_defines_common.h | 46 ++-
src/intel/compiler/brw_eu_defines.h | 22 +
3 files changed, 48 insertions(+), 21 deletions
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.am | 12
src/mesa/drivers/dri/i965/Makefile.sources | 9 +
src/mesa/drivers/dri/i965/brw_state.h | 1 +
3 files changed, 22 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
Emit 3DSTATE_MULTISAMPLE using brw_batch_emit.
v3:
- Remove dead code (Ken)
- Simplify #if/#endif (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h| 9 +-
src/mesa/drivers/dri/i965/brw_state.h | 2
Emits 3DSTATE_RASTER from genX_state_upload.c using pack structs from
genxml.
v3:
- Style fixes (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen8_sf_state.c | 125
Emit 3DSTATE_SOL on Gen7+ using brw_batch_emit helper, that uses pack
structs from genxml.
v2:
- Add helpers to assign struct brw_address (Kristian)
v3:
- Rename MOCS -> SOBufferMOCS
- Do not re-declare MOCS macros (Ken).
- Style and code reorganization (Ken).
Signed-off-by: Raf
Emit clip state on Gen6+ using brw_batch_emit helper, using pack structs
from genxml.
v3:
- Lots style fixes (Ken)
- Do not set CullTestEnableBitMask on Gen8+ (Ken)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965
Upload blend states using GENX(BLEND_STATE_ENTRY_pack), generated from
genxml.
v3:
- style fixes (Ken)
- cleanup to remove excessive #ifdef's (Ken)
- remove memset (Ken)
- disable blend.AlphaToCoverageDitherEnable on gen6 (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Ke
That helper function returns the line width as a float, and is then used
by brw_get_line_width to return the fixed point width.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_util.h | 25 ++---
1 file changed, 14 insertions
- "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid"
- "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer"
- "BackFace" -> "Backface"
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
--
On this patch, we port:
- brw_polygon_stipple
- brw_polygon_stipple_offset
- brw_line_stipple
- brw_drawing_rect
v2:
- Also emit states for gen4-5 with this code.
v3:
- Style fixes and remove excessive checks (Ken).
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri
Emit 3DSTATE_SCISSOR_STATE_POINTERS using brw_batch_emit, and pack the
scissor states using GENX(SCISSOR_RECT_pack), generated from genxml.
v3:
- Remove old code (Ken)
- Style fixes (Ken)
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965
nes.h.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 41 +-
src/mesa/drivers/dri/i965/brw_defines.h | 42 +--
2 files changed, 41 insertions(+), 42 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src
In a previous patch some enums were split out from brw_eu_defines.h, so
they could be used by genxml based code. anv can also benefit from this.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/genX_pipeline.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/intel
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/genxml/gen6.xml | 2 +-
src/intel/genxml/gen7.xml | 2 +-
src/intel/genxml/gen75.xml| 2 +-
src/intel/genxml/gen8.xml | 2 +-
src/intel/genxml
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 +-
src/mesa/drivers/dri/i965/brw_state.h | 1 +-
src/mesa/drivers/dri/i965/gen6_cc.c | 90 +
src/mesa/drivers/dri/i965/genX_state_upload.c | 53 +++-
4 files
On Tue, May 02, 2017 at 09:38:53AM +0100, Emil Velikov wrote:
> On 2 May 2017 at 09:32, Emil Velikov wrote:
> > Hi Rafael,
> >
> > On 2 May 2017 at 02:43, Rafael Antognolli
> > wrote:
> >> We need to use some enums inside genX_state_upload.c, but includ
On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote:
> On Mon, May 1, 2017 at 6:43 PM, Rafael Antognolli
>
> wrote:
>
> We need to use some enums inside genX_state_upload.c, but including the
> whole header will cause several conflicts between thin
On Tue, May 02, 2017 at 08:44:05AM -0700, Jason Ekstrand wrote:
> On Tue, May 2, 2017 at 8:28 AM, Rafael Antognolli
>
> wrote:
>
> On Tue, May 02, 2017 at 07:26:53AM -0700, Jason Ekstrand wrote:
> > On Mon, May 1, 2017 at 6:43 PM, Rafael Antognolli <
>
These enums live inside struct brw_wm_prog_data, so it makes sense to
keep them in the same header. It also allows to use them without
including brw_eu_defines.h.
Signed-off-by: Rafael Antognolli
---
src/intel/compiler/brw_compiler.h | 21 +
src/intel/compiler
Since the enum is in the same header now, we can use it as the type of
the field.
Signed-off-by: Rafael Antognolli
---
PS: We can merge this with the previous patch too if that's better.
src/intel/compiler/brw_compiler.h | 2 +-
src/intel/compiler/brw_fs.cpp | 2 +-
2 files chang
Patch is
Reviewed-by: Rafael Antognolli
On Mon, May 01, 2017 at 01:54:49PM -0700, Matt Turner wrote:
> Newer Gens' names don't have the brackets. Having common names will make
> some later patches simpler.
> ---
> src/intel/genxml/gen4.xml | 2 +-
> src/intel/genxm
Reviewed-by: Rafael Antognolli
On Mon, May 01, 2017 at 01:54:52PM -0700, Matt Turner wrote:
> ---
> src/intel/common/gen_decoder.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
Reviewed-by: Rafael Antognolli
On Fri, Apr 28, 2017 at 05:04:05PM -0700, Kenneth Graunke wrote:
> The Ironlake documentation is terrible, so it's unclear whether or not
> this field exists there. It definitely doesn't exist on Sandybridge
> and later. It definitely does ex
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