[Mesa-dev] [PATCH v2 3/3] i965/fs: emit MOV_INDIRECT with the source with the right register type

This was hiding bugs as it retyped the source to destination's type. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.0" <mesa-sta...@lists.freedesktop.org> Reviewed-by: Francisco Jerez <curroje...@riseup.net> --- src/mesa/drivers/dri/i965/br

[Mesa-dev] [PATCH v2 1/3] i965/fs: fix indirect load DF uniforms on BSW/BXT

and the emitted machine code. v2: - Improve commit log (Curro) - Fix read_size (Curro) - Fix DF uniform array detection in assign_constant_locations() when it is acceded with 32-bit MOV_INDIRECTs in BSW/BXT. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.0

Re: [Mesa-dev] [PATCH v3 08/24] i965/fs: fix dst stride in IVB/BYT type conversions

On Thu, 2017-02-16 at 08:11 +0100, Samuel Iglesias Gonsálvez wrote: > On Wed, 2017-02-15 at 12:08 -0800, Francisco Jerez wrote: > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com&g

Re: [Mesa-dev] [PATCH v3 08/24] i965/fs: fix dst stride in IVB/BYT type conversions

On Wed, 2017-02-15 at 12:08 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > When converting a DF to 32-bit conversions, we set dst stride to 2,

Re: [Mesa-dev] [PATCH v3 06/24] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

On Wed, 2017-02-15 at 11:45 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: Matt Turner <matts...@gmail.com> > > > > On HSW+, scalar DF sources can be accessed using the normal <0,1,0> >

Re: [Mesa-dev] [PATCH v3 04/24] i965/fs: double regioning parameters and execsize for DF in IVB/BYT

On Wed, 2017-02-15 at 11:41 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > In IVB and BYT, both regioning parameters and execution size

Re: [Mesa-dev] [Mesa-stable] [PATCH 1/2] i965/fs: fix indirect load DF uniforms on BSW/BXT

On Tue, 2017-02-14 at 11:11 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Previously we were emitting two MOV_INDIRECT instructions by > > calculating > > source's indirect offsets for each 32-bit ha

Re: [Mesa-dev] [PATCH 3/3] nir: handle some 64-bit integer conversions

   case nir_type_bool: >        assert(dst == nir_type_float64); >    return nir_op_u2d; You missed boolean to [u]int64 conversion but it can be added in a follow-up patch. In either case: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > @@ -2038,4 +2049,5 @@

Re: [Mesa-dev] [PATCH 2/3] nir: handle 64-bit integer types in glsl->nir type conversion.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Wed, 2017-02-15 at 18:43 +1000, Dave Airlie wrote: > From: Dave Airlie <airl...@redhat.com> > > Signed-off-by: Dave Airlie <airl...@redhat.com> > --- >  src/compiler/nir/nir.h | 6 ++ >  1 fil

[Mesa-dev] [PATCH v3 24/24] docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 5905dba9b39..bb2bf884626 100644 --- a/docs/features.txt +++ b/docs/features.txt @@

[Mesa-dev] [PATCH v3 22/24] i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index f1290

[Mesa-dev] [PATCH v3 21/24] i965: Use correct VertStride on align16 instructions.

<1>DFg1<0>.xyxyDF-g9<2>DF{ align16 2N }; ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed v2: - Add spec quote (Curro). - Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro) Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia

[Mesa-dev] [PATCH v3 23/24] i965: enable OpenGL 4.0 to Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++ src/mesa/drivers/dri/i965/intel_screen.c | 6 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/sr

[Mesa-dev] [PATCH v3 17/24] i965/vec4: consider subregister offset in live variables

From: "Juan A. Suarez Romero" Take into account offset values less than a full register (32 bytes) when getting the var from register. This is required when dealing with an operation that writes half of the register (like one d2x in IVB/BYT, which uses exec_size == 4). -

[Mesa-dev] [PATCH v3 18/24] i965/vec4: adapt setup_imm_df() to allow inserting instructions before another one

Add a new setup_imm_df() that allows the insertion of the instructions before another one. This will be used in the lowering passes for DF instructions. v2: - Adapt emission of DIM instruction too. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH v3 20/24] i965/vec4: Fix exec size for MOVs SET_{HIGH, LOW}_32BIT.

rom the two source registers must be the same The intention was to emit mov(4)s for the instructions that have ERROR annotations. See tests/spec/arb_gpu_shader_fp64/execution/vs-isinf-dvec.shader_test for example. Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/d

[Mesa-dev] [PATCH v3 11/24] i965/fs: Get 64-bit indirect moves working on IVB.

From: Francisco Jerez <curroje...@riseup.net> Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 27 -- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/mesa/driv

[Mesa-dev] [PATCH v3 15/24] i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT

From: "Juan A. Suarez Romero" In the generator we must generate slightly different code for Ivybridge/Baytrail, because of the way the stride works in this hardware. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 - 1 file changed, 16

[Mesa-dev] [PATCH v3 19/24] i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with conditional modifiers

ring without any problem. v2: - Fix typo (Matt) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 80 +++--- 1 file changed, 74 insertions(+), 6

[Mesa-dev] [PATCH v3 13/24] i965/vec4: split DF instructions and later double its execsize in IVB/BYT

We need to split DF instructions in two on IVB/BYT as it needs an execsize 8 to process 4 DF values (one GRF in total). v2: - Rename helper and make it static inline function (Matt). - Fix indention and add braces (Matt). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --

[Mesa-dev] [PATCH v3 16/24] i965/vec4: fix SIMD-width lowering for VEC4_OPCODE_FROM_DOUBLE in IVB/BYT

From: "Juan A. Suarez Romero" When splitting VEC4_OPCODE_FROM_DOUBLE in Ivybridge/Baytrail, the second part should use a temporal register, and then move the values to the second half of the original destination, so we get all the results in the same register. v2: - Fix

[Mesa-dev] [PATCH v3 06/24] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

g() (Curro). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index b

[Mesa-dev] [PATCH v3 10/24] i965: Use source region <1, 2, 0> when converting to DF.

From: Matt Turner <matts...@gmail.com> Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead of two. Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +++- src/mesa/driv

[Mesa-dev] [PATCH v3 14/24] i965/vec4: keep original type when dealing with null registers

From: "Juan A. Suarez Romero" Keep the original type when dealing with null registers. Specially because we do no want to introduce an implicit conversion between types that could affect the conditional flags. This affects specially when the original type is DF, and we are

[Mesa-dev] [PATCH v3 07/24] i965/fs: generalize the legalization d2x pass

Add support to SEL instruction and add an assert to detect unsupported instructions than do d2x conversions. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- Curro, this patch legalizes SEL instruction too. If other optimizations modify later any SEL's (or any

[Mesa-dev] [PATCH v3 08/24] i965/fs: fix dst stride in IVB/BYT type conversions

rro) Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 76 +++--- 1 file changed, 45 insertions(+), 31 deletions(-) diff --git

[Mesa-dev] [PATCH v3 09/24] i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

d by the number of address registers that are available, but by the EU decompression logic not handling VxH indirect addressing correctly. This patch limits the SIMD width to 4 in this case. v2: - Fix typo (Matt). - Fix condition (Curro) v3: - Add spec quote (Curro) Signed-off-by: Samuel Iglesias Gonsá

[Mesa-dev] [PATCH v3 12/24] i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT

The hardware applies the same channel enable signals to both halves of the compressed instruction which will be just wrong under non-uniform control flow. Fix this by splitting those instructions to SIMD4. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Fra

[Mesa-dev] [PATCH v3 05/24] i965/fs: clamp exec_size when an instruction has a scalar DF source

Then the SIMD lowering pass will get rid of any compressed instructions with scalar source (whether force_writemask_all or not) and we avoid hitting the Gen7 region decompression bug. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Suggested-by: Francisco Jerez &l

[Mesa-dev] [PATCH v3 01/24] i965/disasm: also print nibctrl in IVB for execsize=8

From: Iago Toral Quiroga 4-wide DF operations where NibCtrl applies require and execsize of 8 in IvyBridge/BayTrail. v2: - Refactor NibCtrl printing (Matt) Reviewed-by: Matt Turner Reviewed-by: Francisco Jerez ---

[Mesa-dev] [PATCH v3 02/24] i965: Handle IVB DF differences in the validator.

From: Matt Turner <matts...@gmail.com> On IVB/BYT, region parameters and execution size for DF are in terms of 32-bit elements, so they are doubled. For evaluating the validity of an instruction, we halve them. v2 (Sam): - Add comments. Reviewed-by: Samuel Iglesias Gonsálvez &

[Mesa-dev] [PATCH v3 04/24] i965/fs: double regioning parameters and execsize for DF in IVB/BYT

vinfo directly (Matt). - Use Baytrail instead of Valleview (Matt). - Use IvyBridge instead of Ivy (Matt) - Double the exec_size in code emission (Curro) v3: - Change hstride doubling by an assert and fix commit log (Curro). - Substitute remaining compiler->devinfo by devinfo (Curro). Signed-of

[Mesa-dev] [PATCH v3 00/24] i965 Ivybridge ARB_gpu_shader_fp64 / OpenGL 4.0

t VertStride on align16 instructions. Samuel Iglesias Gonsálvez (8): i965/fs: clamp exec_size when an instruction has a scalar DF source i965/fs: generalize the legalization d2x pass i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT i965/vec4: split DF instructio

[Mesa-dev] [PATCH v3 03/24] i965/fs: add helper to retrieve instruction data size

po in commit log (Matt) - Use static inline function instead of fs_inst's method (Curro). - Define the result as a constant (Curro). - Fix indentation (Matt). - Add braces to nested control flow (Matt). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Reviewed-by: Francisco Jerez

[Mesa-dev] [PATCH 2/2] i965/fs: emit MOV_INDIRECT with the source with the right register type

This was hiding bugs as it retyped the source to destination's type. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Cc: "17.0" <mesa-sta...@lists.freedesktop.org> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +- 1 file changed, 1 insertion(+), 1 d

[Mesa-dev] [PATCH 1/2] i965/fs: fix indirect load DF uniforms on BSW/BXT

Previously we were emitting two MOV_INDIRECT instructions by calculating source's indirect offsets for each 32-bit half of a DF source. However, this is not needed as we can just emit two 32-bit MOV INDIRECT without doing that calculation. Signed-off-by: Samuel Iglesias Gonsálvez <sig

Re: [Mesa-dev] [PATCHv3 09/20] i965/fs: Get 64-bit indirect moves working on IVB.

On Fri, 2017-02-10 at 10:44 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Thu, 2017-02-09 at 18:28 -0800, Francisco Jerez wrote: > > > Francisco Jerez <curroje...@riseup.net> writes: > > > > >

Re: [Mesa-dev] [PATCH v2 09/20] i965/fs: indirect addressing with doubles is not supported in IVB/BYT

On Fri, 2017-02-10 at 10:10 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Thu, 2017-02-09 at 12:18 -0800, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > >

[Mesa-dev] [PATCH] i965/fs: fix 32-bit data type to int64 conversion on BSW/BXT

The 32-bit to 64-bit conversions need to have the 32-bit data source elements aligned to 64-bit but only with doubles as destination type. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Tested-by: Mark Janes <

Re: [Mesa-dev] [PATCH v2 09/20] i965/fs: indirect addressing with doubles is not supported in IVB/BYT

On Thu, 2017-02-09 at 12:18 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > It is tested empirically that IVB/BYT don't support indirect > > addressing > > with doubles but it is not documented in the PRM. > &

Re: [Mesa-dev] [PATCHv3 09/20] i965/fs: Get 64-bit indirect moves working on IVB.

On Thu, 2017-02-09 at 18:28 -0800, Francisco Jerez wrote: > Francisco Jerez writes: > > > --- > > This replaces "[PATCH v2 09/20] i965/fs: indirect addressing with > > doubles is not supported in IVB/BYT". > > > > Note that some of the fp64 indirect addressing test-cases

Re: [Mesa-dev] [PATCHv3 09/20] i965/fs: Get 64-bit indirect moves working on IVB.

devinfo, brw_last_inst, true); > + > + brw_ADD(p, spread(suboffset(addr, 1), 2), > indirect_byte_offset, > + brw_imm_uw(imm_byte_offset + 4)); > + brw_inst_set_no_dd_check(devinfo, brw_last_inst, true); > + > + brw_pop_insn_state(p); > +  } &

[Mesa-dev] [PATCH 2/2] glsl: refactor get_variable_being_redeclared() to return always an ir_variable pointer

It will return the current variable ('var') or the earlier declaration ('earlier') in case of redeclaration of that variable. In order to distinguish between both, 'is_redeclaration' boolean will indicate in which case we are. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.

[Mesa-dev] [PATCH 1/2] glsl: fix heap-use-after-free in ast_declarator_list::hir()

in ast_declarator_list::hir(). This patch fixes it by picking the ir_variable_mode from the proper ir_variable. This error was detected by Address Sanitizer. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Suggested-by: Ian Romanick <ian.d.roman...@intel.com> Bugzilla: https://bugs.fre

Re: [Mesa-dev] [PATCH v2] glsl: fix heap-use-after-free in ast_declarator_list::hir()

; ast_declarator_list::hir(). > > > > This patch fixes it by assign the pointer 'var' to the pointer > > 'earlier'. > > > > This error was detected by Address Sanitizer. > > > > v2: > > > > * Pointer-to-pointer assignment (Bartosz Tomczyk) >

[Mesa-dev] [PATCH 5/7] i965/fs: Add support for nir_op_[iu]2[iu]32

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 7/7] i965/fs: add support for int64 to bool conversion

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_n

[Mesa-dev] [PATCH 6/7] nir: add opcode to perform int64 to bool conversions

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 --- src/compiler/glsl/glsl_to_nir.cpp | 1 + src/compiler/nir/nir_opcodes.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.

[Mesa-dev] [PATCH 2/7] i965/fs: Add support for nir_op_[iu]642d

From: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index e0c2fa01ce3..a0636596318 100644 ---

[Mesa-dev] [PATCH 3/7] i965/fs: legalize [u]int64 to 32-bit data conversions in lower_d2x

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 --- src/mesa/drivers/dri/i965/brw_fs_lower_d2x.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_lower_d2x.

[Mesa-dev] [PATCH 4/7] i965/fs: Add support for nir_op_[iu]642f

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660 --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dr

[Mesa-dev] [PATCH 1/7] i965: Allow int64 conversion operations in channel_expressions

From: Jason Ekstrand This fixes 143 of the new piglit tests added by Nicolai Cc: Ian Romanick --- .../dri/i965/brw_fs_channel_expressions.cpp| 48 +++--- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git

[Mesa-dev] [PATCH v2] glsl: fix heap-use-after-free in ast_declarator_list::hir()

in ast_declarator_list::hir(). This patch fixes it by assign the pointer 'var' to the pointer 'earlier'. This error was detected by Address Sanitizer. v2: * Pointer-to-pointer assignment (Bartosz Tomczyk) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99677 Signed-off-by: Samuel Iglesias Gonsálvez

Re: [Mesa-dev] [PATCH] glsl: fix heap-use-after-free in ast_declarator_list::hir()

nd a v2. Thanks! > On Tue, Feb 7, 2017 at 11:45 AM, Samuel Iglesias Gonsálvez @igalia.com> wrote: > > The get_variable_being_redeclared() function can free 'var' because > > > > a re-declaration of an unsized array variable can establish the > > size, so > > &

Re: [Mesa-dev] [PATCH] glsl: fix heap-use-after-free in ast_declarator_list::hir()

e_being_redeclared() signature: static ir_variable * get_variable_being_redeclared(ir_variable *var, YYLTYPE loc,   struct _mesa_glsl_parse_state *state,   bool allow_all_redeclarations) Sam > On Tue, Feb 7, 2017 at 11:45 AM, Samuel Iglesia

[Mesa-dev] [PATCH] glsl: fix heap-use-after-free in ast_declarator_list::hir()

in ast_declarator_list::hir(). This patch fixes it by assigning 'earlier' to var, as this variable is the one we keep. This error was detected by Address Sanitizer. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99677 Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compile

Re: [Mesa-dev] [PATCH] spirv: Add more asserts in vtn_vector_construct

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-02-06 at 21:20 -0800, Jason Ekstrand wrote: > On Mon, Feb 6, 2017 at 9:18 PM, Jason Ekstrand <ja...@jlekstrand.net> > wrote: > > These are currently getting hit by the Skia Vulkan back-

Re: [Mesa-dev] [PATCH] i965/fs: don't lower different type size conversions on opt_peephole_sel()

Gentle reminder :) Sam On Wed, 2017-01-25 at 11:20 +0100, Samuel Iglesias Gonsálvez wrote: > Don't lower a type conversion between different type sizes > because SEL does't support them, SEL without conditional modifier > just do a raw move. > > Signed-off-by: Samuel Iglesias Go

Re: [Mesa-dev] [PATCH] mesa: Don't crash when destroying contexts created with no visual.

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Thu, 2017-02-02 at 13:14 -0800, Kenneth Graunke wrote: > dEQP-EGL.functional.create_context.no_config tries to create a > context > with no config, then immediately destroys it.  The drawbuffer is > never >

Re: [Mesa-dev] [PATCH] anv/pass: Store the depth-stencil attachment's last subpass index

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Wed, 2017-02-01 at 17:21 -0800, Nanley Chery wrote: > Commit 968ffd6c868af7226e8f889573eef709888151cb stored the last > subpass > index of all the attachments but that of the depth-stencil > attachment. > T

Re: [Mesa-dev] [PATCH 1/5] intel/isl: Rename supports_lossless_compression to supports_ccs_e

Patch series is Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Just one minor comment on patch 3. Sam On Wed, 2017-02-01 at 14:40 -0800, Jason Ekstrand wrote: > The term "lossless compression" could potentially mean multisample > color compressio

Re: [Mesa-dev] [PATCH 3/5] intel/isl: Add a formats_are_ccs_e_compatible helper

   enum isl_format format1, > + enum isl_format format2) > +{ > +   /* They must support CCS_E */ > +   if (!isl_format_supports_ccs_e(devinfo, format1) || > +   !isl_format_supports_ccs_e(devinfo, format1)) s/format1/format2 Wi

Re: [Mesa-dev] [PATCH v2 09/20] i965/fs: indirect addressing with doubles is not supported in IVB/BYT

On Mon, 2017-01-23 at 15:52 +0100, Samuel Iglesias Gonsálvez wrote: > On Fri, 2017-01-20 at 13:41 -0800, Matt Turner wrote: > > On Tue, Jan 17, 2017 at 1:49 AM, Samuel Iglesias Gonsálvez > > <sigles...@igalia.com> wrote: > > > It is tested empirically that

[Mesa-dev] [PATCH] i965/fs: don't lower different type size conversions on opt_peephole_sel()

Don't lower a type conversion between different type sizes because SEL does't support them, SEL without conditional modifier just do a raw move. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 2 ++ 1 file chan

Re: [Mesa-dev] [PATCH v2 09/20] i965/fs: indirect addressing with doubles is not supported in IVB/BYT

On Fri, 2017-01-20 at 13:41 -0800, Matt Turner wrote: > On Tue, Jan 17, 2017 at 1:49 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > It is tested empirically that IVB/BYT don't support indirect > > addressing > > with doubles but i

Re: [Mesa-dev] [PATCH 3/3] i965: Use correct VertStride on align16 instructions.

On Fri, 2017-01-20 at 14:25 -0800, Francisco Jerez wrote: > Matt Turner writes: > > > In commit c35fa7a, we changed the "width" of DF source registers to > > 2, > > which is conceptually fine. Unfortunately a VertStride of 2 is not > > allowed by align16 instructions on

Re: [Mesa-dev] [PATCH 0/3] i965: IVB/BYT fp64 fixes

On Fri, 2017-01-20 at 13:35 -0800, Matt Turner wrote: > I committed my EU validator earlier today. It's caught three bugs in > the IVB > fp64 series. Patches 2 and 3 fix two of them. I'll respond directly > to the > patch in Igalia's series that introduces the other bug. > OK, while waiting for

Re: [Mesa-dev] [PATCH v2 06/20] i965/fs: fix dst stride in IVB/BYT type conversions

On Thu, 2017-01-19 at 15:00 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Wed, 2017-01-18 at 12:44 -0800, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > >

Re: [Mesa-dev] [PATCH v2 06/20] i965/fs: fix dst stride in IVB/BYT type conversions

On Thu, 2017-01-19 at 11:06 -0800, Matt Turner wrote: > On Thu, Jan 19, 2017 at 4:50 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > As we are blocking the release and there more patches for review, > > another possibility is to land this patch [2] (

Re: [Mesa-dev] [PATCH v2 06/20] i965/fs: fix dst stride in IVB/BYT type conversions

On Wed, 2017-01-18 at 12:44 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > On Tue, 2017-01-17 at 13:26 -0800, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > &g

Re: [Mesa-dev] [PATCH v2 05/20] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

On Wed, 2017-01-18 at 11:39 -0800, Matt Turner wrote: > On Wed, Jan 18, 2017 at 2:45 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.com> wrote: > > On Tue, 2017-01-17 at 13:33 -0800, Francisco Jerez wrote: > > > Samuel Iglesias Gonsálvez <sigles...@igalia.com>

Re: [Mesa-dev] [PATCH v2 06/20] i965/fs: fix dst stride in IVB/BYT type conversions

On Tue, 2017-01-17 at 13:26 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > When converting a DF to F, we set dst stride to 2, to fulfil >

Re: [Mesa-dev] [PATCH v2 03/20] i965/fs: double regioning parameters and execsize for DF in IVB/BYT

On Tue, 2017-01-17 at 14:04 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > In IVB and BYT, both regioning parameters and execution sizes are &

Re: [Mesa-dev] [PATCH v2 07/20] i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

On Tue, 2017-01-17 at 14:15 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: "Juan A. Suarez Romero" <jasua...@igalia.com> > > > > Previous to Broadwell, we have 8 registers for MOV_INDIRE

Re: [Mesa-dev] [PATCH v2 05/20] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

On Tue, 2017-01-17 at 13:33 -0800, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > From: Matt Turner <matts...@gmail.com> > > > > On HSW+, scalar DF sources can be accessed using the normal <0,1,0> >

Re: [Mesa-dev] [PATCH v2 04/20] i965/fs: clamp exec_size to 4 when an instruction has an scalar DF source

On Tue, 2017-01-17 at 12:26 -0800, Francisco Jerez wrote: > Typo in the subject line "an scalar". > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > > > Then the SIMD lowering pass will get rid of any compressed > > instructions with scalar

[Mesa-dev] [PATCH v2 17/20] i965/vec4: fix SIMD-with lowering for CMP/MOV instructions with conditional modifiers

ring without any problem. v2: - Fix typo (Matt) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 80 +++--- 1 file changed, 74 insertions(+), 6

[Mesa-dev] [PATCH v2 16/20] i965/vec4: adapt setup_imm_df() to allow inserting instructions before another one

Add a new setup_imm_df() that allows the insertion of the instructions before another one. This will be used in the lowering passes for DF instructions. v2: - Adapt emission of DIM instruction too. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH v2 15/20] i965/vec4: consider subregister offset in live variables

From: "Juan A. Suarez Romero" Take in account the offset value when getting the var from register. This is required when dealing with an operation that writes half of the register (like one d2x in IVB/BYT, which uses exec_size == 4). Note that for live analysis variables

[Mesa-dev] [PATCH v2 18/20] i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index b674b

[Mesa-dev] [PATCH v2 19/20] i965: enable OpenGL 4.0 to Ivybridge/Baytrail

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 ++ src/mesa/drivers/dri/i965/intel_screen.c | 6 -- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/sr

[Mesa-dev] [PATCH v2 20/20] docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- docs/features.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index aff00167dc9..c746277678c 100644 --- a/docs/features.txt +++ b/docs/features.txt @@

[Mesa-dev] [PATCH v2 13/20] i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYT

From: "Juan A. Suarez Romero" In the generator we must generate slightly different code for Ivybridge/Baytrail, because of the way the stride works in this hardware. --- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 17 - 1 file changed, 16

[Mesa-dev] [PATCH v2 11/20] i965/vec4: split DF instructions and later double its execsize in IVB/BYT

We need to split DF instructions in two on IVB/BYT as it needs an execsize 8 to process 4 DF values (one GRF in total). v2: - Rename helper and make it static inline function (Matt). - Fix indention and add braces (Matt). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --

[Mesa-dev] [PATCH v2 09/20] i965/fs: indirect addressing with doubles is not supported in IVB/BYT

assert to take into account Indirect DF MOVs in IVB and HSW. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 27 ++ src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ++- 2 files chang

[Mesa-dev] [PATCH v2 10/20] i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT

The hardware applies the same channel enable signals to both halves of the compressed instruction which will be just wrong under non-uniform control flow. Fix this by splitting those instructions to SIMD4. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drive

[Mesa-dev] [PATCH v2 12/20] i965/vec4: keep original type when dealing with null registers

From: "Juan A. Suarez Romero" Keep the original type when dealing with null registers. Specially because we do no want to introduce an implicit conversion between types that could affect the conditional flags. This affects specially when the original type is DF, and we are

[Mesa-dev] [PATCH v2 14/20] i965/vec4: fix SIMD-width lowering for VEC4_OPCODE_FROM_DOUBLE in IVB/BYT

From: "Juan A. Suarez Romero" When splitting VEC4_OPCODE_FROM_DOUBLE in Ivybridge/Baytrail, the second part should use a temporal register, and then move the values to the second half of the original destination, so we get all the results in the same register. v2: - Fix

[Mesa-dev] [PATCH v2 02/20] i965/fs: add helper to retrieve instruction data size

po in commit log (Matt) - Use static inline function instead of fs_inst's method (Curro). - Define the result as a constant (Curro). - Fix indentation (Matt). - Add braces to nested control flow (Matt). Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dr

[Mesa-dev] [PATCH v2 03/20] i965/fs: double regioning parameters and execsize for DF in IVB/BYT

doubles. We need to double the parameters to cope with this issue. v2: - Use devinfo directly (Matt). - Use Baytrail instead of Valleview (Matt). - Use IvyBridge instead of Ivy (Matt) - Double the exec_size in code emission (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com&

[Mesa-dev] [PATCH v2 06/20] i965/fs: fix dst stride in IVB/BYT type conversions

From: "Juan A. Suarez Romero" When converting a DF to F, we set dst stride to 2, to fulfil alignment restrictions. But in IVB/BYT, this is not necessary, as each DF conversion already writes 2 F, the first one the real value, and the second one a 0. That is, IVB/BYT already

[Mesa-dev] [PATCH v2 04/20] i965/fs: clamp exec_size to 4 when an instruction has an scalar DF source

Then the SIMD lowering pass will get rid of any compressed instructions with scalar source (whether force_writemask_all or not) and we avoid hitting the Gen7 region decompression bug. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Suggested-by: Francisco Jerez &l

[Mesa-dev] [PATCH v2 05/20] i965: Use <0, 2, 1> region for scalar DF sources on IVB/BYT.

From: Matt Turner On HSW+, scalar DF sources can be accessed using the normal <0,1,0> region, but on IVB and BYT DF regions must be programmed in terms of floats. A <0,2,1> region accomplishes this. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 26 --

[Mesa-dev] [PATCH v2 01/20] i965/disasm: also print nibctrl in IVB for execsize=8

From: Iago Toral Quiroga 4-wide DF operations where NibCtrl applies require and execsize of 8 in IvyBridge/BayTrail. v2: - Refactor NibCtrl printing (Matt) Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++--- 1 file changed, 3

[Mesa-dev] [PATCH v2 07/20] i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

irect addressing correctly. This patch limits the SIMD width to 4 in this case. v2: - Fix typo (Matt). - Fix condition (Curro) Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com> --- src/mesa/drivers/dri/i965/brw_fs.c

[Mesa-dev] [PATCH v2 08/20] i965: Use source region <1, 2, 0> when converting to DF.

From: Matt Turner Doing so allows us to use a single MOV in VEC4_OPCODE_TO_DOUBLE instead of two. --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +++- src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +-- 2 files changed, 28

Re: [Mesa-dev] [PATCH 05/27] i965: Replace open coded with intel_miptree_get_image_offset()

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote: > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- >  src/mesa/drivers/dri/i965/intel_pixel_read.c | 16 ++-- >  1 fil

Re: [Mesa-dev] [PATCH 02/27] i965/miptree: Remove redundant check for null texture

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote: > There exact same check earlier in brw_miptree_layout() which > intel_miptree_create_layout() in turn calls unconditionally. > > Signed-off-by

Re: [Mesa-dev] [PATCH 03/27] i965: Remove check for hiz on earlier gens than SNB

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote: > Only caller, brw_workaround_depthstencil_alignment(), returns > early for gen6+. > > While at it, reduce scope for brw_get_depthstencil_tile_masks() as &

Re: [Mesa-dev] [PATCH 01/27] i965/meta: Remove unused brw_get_rb_for_slice()

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On Mon, 2017-01-16 at 11:13 +0200, Topi Pohjolainen wrote: > Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com> > --- >  src/mesa/drivers/dri/i965/brw_meta_util.c | 44 --- >

<    1   2   3   4   5   6   7   8   9   10   >