[Mesa-dev] [PATCH 26/59] i965/fs: always pass the bitsize to brw_type_for_nir_type()

From: Connor Abbott v2 (Sam): - Add bitsize to brw_type_for_nir_type() in optimize_extract_to_float() --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp

[Mesa-dev] [PATCH 31/59] i965/fs: optimize pack double

From: Iago Toral Quiroga When we are actually creating a double using values obtained from a previous unpack operation we can bypass the unpack and source from the original double value directly. --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 23 +++ 1

[Mesa-dev] [PATCH 32/59] i965/fs: optimize unpack double

From: Iago Toral Quiroga When we are actually unpacking from a double that we have previously packed from its 32-bit components we can bypass the pack operation and source from its arguments directly. --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 28

[Mesa-dev] [PATCH 28/59] i965/fs: add PACK opcode

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_defines.h | 9 + src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++- src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 1 + src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 1

[Mesa-dev] [PATCH 29/59] i965/fs: add a pass for lowering PACK opcodes

From: Connor Abbott --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_fs.cpp| 5 +++ src/mesa/drivers/dri/i965/brw_fs.h | 1 + src/mesa/drivers/dri/i965/brw_fs_lower_pack.cpp | 59 +

[Mesa-dev] [PATCH 27/59] i965/fs: add a stride helper

From: Connor Abbott Similar to retype() and offset(). --- src/mesa/drivers/dri/i965/brw_ir_fs.h | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index e4f20f4..abda2c3 100644 ---

[Mesa-dev] [PATCH 30/59] i965/fs/nir: translate double pack/unpack

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index 3ed3343..ca1f24f 100644 ---

[Mesa-dev] [PATCH 15/59] i965/eu: add support for DF immediates

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 28 +--- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 4c08883..d2c7189

[Mesa-dev] [PATCH 24/59] i965/fs: don't propagate 64-bit immediates

From: Connor Abbott They can only be used with 1-src instructions, which practically (since we should've constant-propagated away all 1-src instructions with 64-bit immediates in NIR) means that they must be kept in separate MOV's and can't be propagated. ---

[Mesa-dev] [PATCH 12/59] i965: add brw_imm_df

From: Connor Abbott v2 (Iago) - Fixup accessibility in backend_reg Signed-off-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_reg.h| 9 + src/mesa/drivers/dri/i965/brw_shader.h | 1 + 2 files changed, 10 insertions(+) diff

[Mesa-dev] [PATCH 21/59] i965: fixup uniform setup for doubles

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp index 636340a..15d99fa 100644

[Mesa-dev] [PATCH 23/59] i965/fs: use the NIR bit size when creating registers

From: Connor Abbott v2 (Iago): - Squashed bits from 'support double precission constant operands for the implementation of 64-bit emit_load_const'. - Do not use BRW_REGISTER_TYPE_D for all 32-bit registers since that breaks asserts and functionality for

[Mesa-dev] [PATCH 16/59] i965: fix brw_negate_immediate() for doubles

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_shader.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index c459f4a..e5c43d2 100644 ---

[Mesa-dev] [PATCH 09/59] i965/disasm: fix disasm of 3-src doubles

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_disasm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 88bd7a4..c4e3761 100644 ---

[Mesa-dev] [PATCH 18/59] i965: fix brw_saturate_immediate() for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_shader.cpp | 28 ++-- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index d40937b..a063b88

[Mesa-dev] [PATCH 22/59] i965/fs: print writemask_all when it's enabled

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 78f7d40..09e48f0 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 07/59] i965: Determine size of double precision float register

From: Topi Pohjolainen This is used to determine how many registers an instruction reads and writes as well as for offseting register region into a desired component. v2 (Connor): rebase on master Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 13/59] i965: add support for getting/setting DF immediates

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_inst.h | 25 + 1 file changed, 25 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_inst.h b/src/mesa/drivers/dri/i965/brw_inst.h index 0e5f613..f45e564 100644 ---

[Mesa-dev] [PATCH 20/59] i965: two-argument instructions can only use 32-bit immediates

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index d2c7189..395671a 100644 ---

[Mesa-dev] [PATCH 11/59] i965/eu: allow doubles in math instructions

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index e5057a0..4c08883 100644 ---

[Mesa-dev] [PATCH 25/59] i965/fs: add support for printing double immediates

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 09e48f0..6455028 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 19/59] i965: fix brw_abs_immediate() for doubles

From: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_shader.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index a063b88..0bc0bd2 100644 ---

[Mesa-dev] [PATCH 08/59] i965: Tell backend register about double precision type

From: Topi Pohjolainen Signed-off-by: Topi Pohjolainen Signed-off-by: Tapani P\344lli Signed-off-by: Abdiel Janulgue --- src/mesa/drivers/dri/i965/brw_shader.cpp | 3 ++- 1 file

[Mesa-dev] [PATCH 17/59] i965: fix is_zero(), is_one() and is_negative_one() for doubles

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_shader.cpp | 28 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index

[Mesa-dev] [PATCH 14/59] i965: add support for disassembling DF immediates

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_disasm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index c4e3761..d9e531b 100644 ---

[Mesa-dev] [PATCH 10/59] i965/eu: Allow 3-src float ops with doubles

From: Topi Pohjolainen v2: - set 3src_src_type for BRW_REGISTER_TYPE_DF (Connor) Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_eu_emit.c | 24 ++-- 1 file changed, 18 insertions(+), 6

[Mesa-dev] [PATCH 05/59] i965: use pack/unpackDouble lowering

From: Connor Abbott --- src/mesa/drivers/dri/i965/brw_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c index 4830774..9414fa6 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.c +++

[Mesa-dev] [PATCH 06/59] i965: Lower DFRACEXP/DLDEXP

lainen <topi.pohjolai...@intel.com> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_link.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index d4bbd8b..aacf48

[Mesa-dev] [PATCH 01/59] i965: enable lrp lowering for doubles

Broadwell and previous generations does not support lrp instruction operating with doubles. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_compile

[Mesa-dev] [PATCH 03/59] freedreno/ir3: lower lrp when operating with double operands

Lower lrp when operating with double operands because float version of lrp is also lowered. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> CC: Rob Clark <robdcl...@gmail.com> --- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 + 1 file changed, 1 insertion(+) diff

[Mesa-dev] [PATCH 00/59] Initial arb_gpu_shader_fp64 support to the i965 scalar backend

d2b i965/fs: implement d2i and d2u i965/fs: implement i2d and u2d i965/fs: rename our lower_d2f pass to lower_d2x i965/fs/lower_simd_width: Fix registers written for split instructions i965/fs: recognize writes with a subreg_offset > 0 as partial Samuel Iglesias Gonsálvez (7): i

[Mesa-dev] [PATCH 02/59] vc4: lower lrp when operating with double operands

Lower lrp when operating with double operands because float version of lrp is also lowered. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> CC: Eric Anholt <e...@anholt.net> --- src/gallium/drivers/vc4/vc4_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a

[Mesa-dev] [PATCH 04/59] i965: use double lowering pass

From: Connor Abbott <connor.w.abb...@intel.com> v2: also lower trunc, ceil, floor, fract and roundEven (Iago) v3: also lower mod for doubles (Sam) Signed-off-by: Iago Toral Quiroga <ito...@igalia.com> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mes

Re: [Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

tice this change would break vulkan build. I have just added that argument to my build. Thanks, Sam > thanks, > > Mark > > Samuel Iglesias Gonsálvez <sigles...@igalia.com> writes: > >> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.co

[Mesa-dev] [PATCH 2/3] mesa: rename lower_fmod to lower_fmod32

A later patch will add lower_fmod64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir.h | 2 +- src/compiler/nir/nir_opt_algebraic.py| 4 ++-- src/mesa/drivers/dri/i965/brw_compiler.c | 2 +- 3 files chan

[Mesa-dev] [PATCH 3/3] nir/opt_algebraic: lower mod() with doubles operands if lower_fmod64 is enabled

Make this distintion as the drivers might need to lower it inside NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_opt_algebraic.py | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff

[Mesa-dev] [PATCH 1/3] nir/lower_double_ops: lower mod()

There are rounding errors with the division in i965 that affect the mod(x,y) result when x = N * y. Instead of returning '0' it was returning 'y'. This lowering pass fixes those cases. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir

[Mesa-dev] [PATCH v2 2/2] nir: Add lrp lowering for doubles in opt_algebraic

the code to define bit_size information in the opcodes. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_opt_algebraic.py | 9 ++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/co

[Mesa-dev] [PATCH v2 1/2] nir: rename lower_flrp to lower_flrp32

A later patch will add lower_flrp64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir.h | 2 +- src/compiler/nir/nir_opt_algebraic.py | 12 ++-- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 2 +

Re: [Mesa-dev] [PATCH 3/3] nir/algebraic: Support lowering for bot 64 and 32-bit ldexp

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 s/bot/both Patches 1-3 are: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 27/04/16 20:25, Jason Ekstrand wrote: > --- src/compiler/nir/nir_opt_algebraic.py | 31 > ++- 1 file changed, 2

Re: [Mesa-dev] [PATCH 11/13] nir: Add lrp lowering for doubles in opt_algebraic

On 27/04/16 21:18, Jason Ekstrand wrote: > On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> Some hardware (i965 on Broadwell generation, for example) does not support >> natively the execution of lrp instruction with

Re: [Mesa-dev] [PATCH 6/6] nir/algebraic: Add a bit-size validator

mon_class = 0 > + for i in range(nir_op.num_inputs): > +src_class = self._validate_bit_class_up(val.sources[i]) > +if src_class == 0: > + continue > + > + src_type_bits = type_bits(nir_op.input_types[i]) > +if src

Re: [Mesa-dev] [PATCH 2/6] nir/algebraic: Use "uint" instead of "unsigned" for uint types

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 26/04/16 06:39, Jason Ekstrand wrote: > This is consistent with the rename done for the rest of NIR. Currently, > "bool" is the only type specifier used in nir_opt_algebraic.py so this is > really a no-op.

Re: [Mesa-dev] [PATCH 5/6] nir/opt_algebraic: Fix some expressions with ambiguous bit sizes

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 26/04/16 06:39, Jason Ekstrand wrote: > --- > src/compiler/nir/nir_opt_algebraic.py | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/src/compiler/nir/nir_opt_algebraic.py

Re: [Mesa-dev] [PATCH 4/6] nir/search: Respect the bit_size parameter on nir_search_value

= 0; i < num_components; ++i) >new_swizzle[i] = instr->src[src].swizzle[swizzle[i]]; > > + /* If the value has a spefic bit size and it doesn't match, bail */ specific Other than that, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam &g

Re: [Mesa-dev] [PATCH] glsl: Checks for interpolation into its own function.

s/mesa-dev/2016-March/109117.html > and Khronos bug #15671. > Do we have news about this Khronos bug? Are the piglit tests pushed upstream? Assuming no piglit/dEQP regressions, this patch is: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam > Signed-off-by: A

Re: [Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

On 13/04/16 07:23, Samuel Iglesias Gonsálvez wrote: > > > On 12/04/16 17:24, Jason Ekstrand wrote: >> On Apr 12, 2016 1:06 AM, "Samuel Iglesias Gonsálvez" <sigles...@igalia.com> >> wrote: >>> >>> Signed-off-by: Samuel Iglesias Gonsálv

[Mesa-dev] [PATCH] mesa/main: handle double uniform matrices properly

From: "Juan A. Suarez Romero" When computing the offset in the uniform storage table, take into account the size multiplier so double precision matrices are handled correctly. Signed-off-by: Juan A. Suarez Romero --- src/mesa/main/uniform_query.cpp |

Re: [Mesa-dev] [PATCH 12/13] nir: add pack_double_2x32_split_y opcode

Please discard this patch and the following one ("[PATCH 13/13] nir/lower_double_ops: optimize set_exponent()"). We have moved this to i965 backend. Sam On 12/04/16 10:05, Samuel Iglesias Gonsálvez wrote: > From: Iago Toral Quiroga <ito...@igalia.com> > > This is

Re: [Mesa-dev] [PATCH 10/13] nir: verify destination bit size when checking algebraic optimizations

On 24/04/16 06:49, Jason Ekstrand wrote: > On Apr 12, 2016 1:06 AM, "Samuel Iglesias Gonsálvez" <sigles...@igalia.com> > wrote: >> >> Some instructions (like flrp in i965) cannot be lowered depending on the >> bit size because it doesn't support al

Re: [Mesa-dev] [PATCH 06/13] nir/lower_double_ops: lower floor()

On 23/04/16 00:17, Jason Ekstrand wrote: > On Fri, Apr 22, 2016 at 3:13 PM, Jason Ekstrand <ja...@jlekstrand.net> > wrote: > >> >> >> On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez < >> sigles...@igalia.com> wrote: >> >>> F

Re: [Mesa-dev] [PATCH 06/13] nir/lower_double_ops: lower floor()

On 23/04/16 00:13, Jason Ekstrand wrote: > On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> At least i965 hardware does not have native support for floor

Re: [Mesa-dev] [PATCH] i965: don't lower mod() in glsl ir

On 22/04/16 09:34, Kenneth Graunke wrote: > On Friday, April 22, 2016 9:24:01 AM PDT Samuel Iglesias Gonsálvez wrote: >> >> On 22/04/16 08:44, Kenneth Graunke wrote: >>> On Friday, April 22, 2016 7:32:43 AM PDT Samuel Iglesias Gonsálvez wrote: >>>> NI

Re: [Mesa-dev] [PATCH] i965: don't lower mod() in glsl ir

On 22/04/16 08:44, Kenneth Graunke wrote: > On Friday, April 22, 2016 7:32:43 AM PDT Samuel Iglesias Gonsálvez wrote: >> NIR will lower it in nir_opt_algebraic. >> >> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> >> --- >> src/mesa/dr

[Mesa-dev] [PATCH] i965: don't lower mod() in glsl ir

NIR will lower it in nir_opt_algebraic. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/mesa/drivers/dri/i965/brw_link.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index b

[Mesa-dev] [PATCH v2] nir/lower_double_ops: lower trunc()

From: Iago Toral Quiroga At least i965 hardware does not have native support for truncating doubles. v2: - Simplified the implementation significantly. - Fixed the else branch, that was not doing what we wanted. --- src/compiler/nir/nir.h | 1 +

Re: [Mesa-dev] [PATCH 04/13] nir: add a pass to lower some double operations

On 20/04/16 05:31, Jason Ekstrand wrote: > On Tue, Apr 19, 2016 at 6:45 PM, Connor Abbott <cwabbo...@gmail.com> wrote: > >> On Tue, Apr 12, 2016 at 4:05 AM, Samuel Iglesias Gonsálvez >> <sigles...@igalia.com> wrote: >>> From: Connor Abbott <c

Re: [Mesa-dev] [PATCH 04/13] nir: add a pass to lower some double operations

On 19/04/16 23:52, Jason Ekstrand wrote: > On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Connor Abbott <connor.w.abb...@intel.com> >> >> v2: Move to compiler/nir (Iago) >> >> S

Re: [Mesa-dev] [PATCH 01/13] nir/builder: add nir_imm_uint()

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 14/04/16 22:39, Jason Ekstrand wrote: > On Tue, Apr 12, 2016 at 1:05 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Connor Abbott <connor.w.abb...@intel.com> >> >> --- src/c

Re: [Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

On 12/04/16 17:24, Jason Ekstrand wrote: > On Apr 12, 2016 1:06 AM, "Samuel Iglesias Gonsálvez" <sigles...@igalia.com> > wrote: >> >> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> >> --- >> src/compiler/nir/nir_builder.h

[Mesa-dev] [PATCH 08/13] nir/lower_double_ops: lower fract()

From: Iago Toral Quiroga At least i965 hardware does not have native support for fract() on doubles. --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_double_ops.c | 14 ++ 2 files changed, 15 insertions(+) diff --git

[Mesa-dev] [PATCH 12/13] nir: add pack_double_2x32_split_y opcode

From: Iago Toral Quiroga This is useful when we only need to modify the high 32-bit chunk of a double. This is a common case, because this is the part that encodes the exponent which we manipulate in some double lowering passes. Although we can accomplish the same by using

[Mesa-dev] [PATCH 02/13] nir/builder: Add bit_size info to nir_build_imm()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compiler/nir/nir_builder.h | 15 --- src/compiler/nir/nir_lower_system_values.c | 2 +- src/compiler/nir/nir_lower_tex.c | 2 +- 3 files changed, 10 insertions(+), 9 deletions(-)

[Mesa-dev] [PATCH 11/13] nir: Add lrp lowering for doubles in opt_algebraic

Some hardware (i965 on Broadwell generation, for example) does not support natively the execution of lrp instruction with double arguments. Add 'lower_lrp_double' flag to lower this instruction in that case. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compil

[Mesa-dev] [PATCH 13/13] nir/lower_double_ops: optimize set_exponent()

From: Iago Toral Quiroga By using pack_double_2x32_split_y instead of pack_double_2x32 we reduce register pressure since we no longer need to unpack the low 32-bits of the double. --- src/compiler/nir/nir_lower_double_ops.c | 7 +++ 1 file changed, 3 insertions(+), 4

[Mesa-dev] [PATCH 07/13] nir/lower_double_ops: lower ceil()

From: Iago Toral Quiroga At least i965 hardware does not have native support for ceil on doubles. --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_double_ops.c | 27 +++ 2 files changed, 28 insertions(+) diff --git

[Mesa-dev] [PATCH 10/13] nir: verify destination bit size when checking algebraic optimizations

Some instructions (like flrp in i965) cannot be lowered depending on the bit size because it doesn't support all bit sizes. If the bit size field is defined in nir_opt_algebraic.py, take it into account. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compil

[Mesa-dev] [PATCH 05/13] nir/lower_double_ops: lower trunc()

From: Iago Toral Quiroga At least i965 hardware does not have native support for truncating doubles. --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_double_ops.c | 83 + 2 files changed, 84 insertions(+) diff

[Mesa-dev] [PATCH 09/13] nir/lower_double_ops: lower round_even()

From: Iago Toral Quiroga At least i965 hardware does not have native support for round_even() on doubles. --- src/compiler/nir/nir.h | 3 +- src/compiler/nir/nir_lower_double_ops.c | 58 + 2 files changed, 60 insertions(+), 1

[Mesa-dev] [PATCH 06/13] nir/lower_double_ops: lower floor()

From: Iago Toral Quiroga At least i965 hardware does not have native support for floor on doubles. --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_double_ops.c | 29 + 2 files changed, 30 insertions(+) diff --git

[Mesa-dev] [PATCH 03/13] nir/builder: add nir_imm_double()

From: Connor Abbott --- src/compiler/nir/nir_builder.h | 8 1 file changed, 8 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 84fc9bf..5787ba8 100644 --- a/src/compiler/nir/nir_builder.h +++

[Mesa-dev] [PATCH 04/13] nir: add a pass to lower some double operations

From: Connor Abbott v2: Move to compiler/nir (Iago) Signed-off-by: Iago Toral Quiroga --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h | 7 + src/compiler/nir/nir_lower_double_ops.c | 387

[Mesa-dev] [PATCH 00/13] nir: add lowering passes for double ops

/lower_double_ops: lower trunc() nir/lower_double_ops: lower floor() nir/lower_double_ops: lower ceil() nir/lower_double_ops: lower fract() nir/lower_double_ops: lower round_even() nir: add pack_double_2x32_split_y opcode nir/lower_double_ops: optimize set_exponent() Samuel Iglesias Gonsálvez (3

[Mesa-dev] [PATCH 01/13] nir/builder: add nir_imm_uint()

From: Connor Abbott --- src/compiler/nir/nir_builder.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 29b13fb..38a1cf7 100644 --- a/src/compiler/nir/nir_builder.h +++

Re: [Mesa-dev] [PATCH] nir/glsl_to_nir: add bit-size info to add_instr()

This patch is still unreviewed. Sam On 05/04/16 10:29, Samuel Iglesias Gonsálvez wrote: > Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> > --- > > This would replace this patch [0] in the series. > > [0] https://lists.freedesktop.org/archives/mesa-de

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add a flat_inputs field to prog_data

On 06/04/16 19:20, Jason Ekstrand wrote: > On Wed, Apr 6, 2016 at 12:47 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> >> >> On 06/04/16 08:03, Samuel Iglesias Gonsálvez wrote: >>> >>> >>> On 06/04/16 05:12, Ja

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add a flat_inputs field to prog_data

On 06/04/16 09:47, Samuel Iglesias Gonsálvez wrote: > > > On 06/04/16 08:03, Samuel Iglesias Gonsálvez wrote: >> >> >> On 06/04/16 05:12, Jason Ekstrand wrote: >>> --- >>> src/mesa/drivers/dri/i965/brw_compiler.h | 6 ++ >&

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add a flat_inputs field to prog_data

On 06/04/16 08:03, Samuel Iglesias Gonsálvez wrote: > > > On 06/04/16 05:12, Jason Ekstrand wrote: >> --- >> src/mesa/drivers/dri/i965/brw_compiler.h | 6 ++ >> src/mesa/drivers/dri/i965/brw_fs.cpp | 31 >> +++ &

Re: [Mesa-dev] [PATCH 2/2] i965/sf_state: Pull flat_enables out of prog_data

Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 06/04/16 05:12, Jason Ekstrand wrote: > Previously, we were walking over the shader source to figure out which > inputs should be marked flat. Now, we can just pull it out of prog_data. > This is needed for prop

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add a flat_inputs field to prog_data

ear in FS, according to gl_varying_slot) then there would be input_index values higher than 32. With that fixed, Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> Sam > + /** > * Map from gl_varying_slot to the position within the FS setup data > * pa

Re: [Mesa-dev] [PATCH 4/6] glsl: fully split apart buffer block arrays

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 In general, I don't see anything wrong with this series, just minor things in this patch. Once they are fixed and if piglit/dEQP don't complain, add my R-b to this series: Reviewed-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> On 03

[Mesa-dev] [PATCH] nir/glsl_to_nir: add bit-size info to add_instr()

Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- This would replace this patch [0] in the series. [0] https://lists.freedesktop.org/archives/mesa-dev/2016-March/111347.html src/compiler/nir/glsl_to_nir.cpp | 24 ++-- 1 file changed, 14 insertions(

Re: [Mesa-dev] [PATCH v2 22/23] nir: add a pass for lowering (un)pack_double_2x32

On 01/04/16 21:30, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 3:00 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Connor Abbott <connor.w.abb...@intel.com> >> >> v2: Undo unintended change to the signature of >>

Re: [Mesa-dev] [PATCH v2 00/23] NIR: more bit-size related patches

On 01/04/16 22:48, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 2:59 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> Hello, >> >> This is the second version of this patch series [0]. >> >> In case you prefer a repository, it is

Re: [Mesa-dev] [PATCH v2 13/23] nir/glsl_to_nir: set the bit-size in the result of evaluate_rvalue

On 01/04/16 22:45, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 3:00 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> Found while testing UBO loads in scenarios like th

Re: [Mesa-dev] [PATCH v2 23/23] nir: verify destination bit size when checking algebraic optimizations

k on it. > OK. Thanks, Sam > On Thu, Mar 31, 2016 at 3:00 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> Some instructions (like flrp in i965) cannot be lowered depending on the >> bit size because it doesn't support all bit sizes. >> >&

Re: [Mesa-dev] [PATCH v2 03/23] nir: add bit_size info to nir_ssa_undef_instr_create()

On 01/04/16 21:02, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 2:59 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> >> --- >> src/compiler/nir/glsl_to_nir.cpp

Re: [Mesa-dev] [PATCH v2 10/23] nir: handle doubles in nir_deref_get_const_initializer_load()

On 01/04/16 21:11, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 2:59 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Connor Abbott <connor.w.abb...@intel.com> >> >> --- >> src/compiler/nir/nir.c | 5 + >> 1 f

Re: [Mesa-dev] [PATCH v2 09/23] nir/print: add support for printing doubles and bitsize

On 01/04/16 21:09, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 2:59 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Connor Abbott <connor.w.abb...@intel.com> >> >> v2: >> - Squash the printing doubles related patches

Re: [Mesa-dev] [PATCH v2 07/23] nir/lower_load_const_to_scalar: suppport doubles and multiple bit sizes

On 01/04/16 21:06, Jason Ekstrand wrote: > On Thu, Mar 31, 2016 at 2:59 AM, Samuel Iglesias Gonsálvez < > sigles...@igalia.com> wrote: > >> From: Iago Toral Quiroga <ito...@igalia.com> >> >> --- >> src/compiler/nir/nir_lower_load_const_to_scalar.c

Re: [Mesa-dev] [PATCH 27/29] nir/lower_to_source_mod: Skip unsafe operations

of them produce regressions. I don't have a strong opinion here, we can keep the code as it is or use uint64 instead but I prefer to apply it to all of *pack_double* ops to keep consistency. What do you think? Sam > On Mon, Mar 21, 2016 at 8:06 AM, Samuel Iglesias Gonsálvez > <sigles...@igalia.c

Re: [Mesa-dev] [PATCH 07/29] nir/lower_tex: fix get_zero_or_one() to use sized types

On 23/03/16 15:56, Jason Ekstrand wrote: > On Mar 23, 2016 12:32 AM, "Samuel Iglesias Gonsálvez" > <sigles...@igalia.com> wrote: >> >> On 21/03/16 23:40, Jason Ekstrand wrote: >>> On Mon, Mar 21, 2016 at 3:39 PM, Jason Ekstrand >>> <ja...@j

[Mesa-dev] [PATCH v2 23/23] nir: verify destination bit size when checking algebraic optimizations

Some instructions (like flrp in i965) cannot be lowered depending on the bit size because it doesn't support all bit sizes. If the bit size field is defined in nir_opt_algebraic.py, take it into account. Signed-off-by: Samuel Iglesias Gonsálvez <sigles...@igalia.com> --- src/compil

[Mesa-dev] [PATCH v2 22/23] nir: add a pass for lowering (un)pack_double_2x32

From: Connor Abbott v2: Undo unintended change to the signature of nir_normalize_cubemap_coords (Iago). v3: Move to compiler/nir (Iago) v4: Remove Authors from copyright header (Michael Schellenberger) Signed-off-by: Iago Toral Quiroga ---

[Mesa-dev] [PATCH v2 17/23] nir: add i2d and u2d opcodes

From: Iago Toral Quiroga v2: - Assert supports_int and don't fallback to nir_fmov (Jason) --- src/compiler/nir/glsl_to_nir.cpp | 8 src/compiler/nir/nir_opcodes.py | 2 ++ 2 files changed, 10 insertions(+) diff --git a/src/compiler/nir/glsl_to_nir.cpp

[Mesa-dev] [PATCH v2 16/23] nir: add d2i, d2u, d2b opcodes

From: Iago Toral Quiroga --- src/compiler/nir/glsl_to_nir.cpp | 3 +++ src/compiler/nir/nir_opcodes.py | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp index 29133d8..2748766 100644 ---

[Mesa-dev] [PATCH v2 19/23] nir: don't try to scalarize unpack_double_2x32

From: Connor Abbott --- src/compiler/nir/nir_lower_alu_to_scalar.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/nir/nir_lower_alu_to_scalar.c b/src/compiler/nir/nir_lower_alu_to_scalar.c index e8ba640..1548abb 100644 ---

[Mesa-dev] [PATCH v2 15/23] nir: add support for d2f and f2d

From: Connor Abbott --- src/compiler/nir/glsl_to_nir.cpp | 2 ++ src/compiler/nir/nir_opcodes.py | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp index 186937d..29133d8 100644 ---

[Mesa-dev] [PATCH v2 20/23] nir: add split versions of (un)pack_double_2x32

From: Connor Abbott --- src/compiler/nir/nir_opcodes.py | 36 1 file changed, 36 insertions(+) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index 12b668f..11da111 100644 ---

[Mesa-dev] [PATCH v2 18/23] nir: add support for (un)pack_double_2x32

From: Connor Abbott --- src/compiler/nir/glsl_to_nir.cpp | 6 ++ src/compiler/nir/nir_opcodes.py | 28 2 files changed, 34 insertions(+) diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp index

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