On Tue, Aug 13, 2013 at 07:04:56PM +0200, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
Also use ordered comparisons for old cmp instructions. Untested.
This patch looks good to me, but I would like to do a piglit run on
radeonsi before you commit. I will try to do
://bugs.freedesktop.org/show_bug.cgi?id=66974
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Michel Dänzer michel.daen...@amd.com
I took a look through the LLVM calls in these patches and they look OK
to me.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
v2: No need to export
Hi,
The attached patches expand a few more vector operations and also move the
expansion code into AMDGPUISelLowering.cpp so it can be shared between R600 and
SI.
-Tom
From a519e387c262ecc0282eb8cb1e2c8802725591b4 Mon Sep 17 00:00:00 2001
From: Tom Stellard thomas.stell...@amd.com
Date: Fri, 2
On Sat, Aug 10, 2013 at 08:50:31PM +0200, Marek Olšák wrote:
Signed-off-by: Marek Olšák marek.ol...@amd.com
You will need to add a test case to this commit, but otherwise the whole
series is:
Reviewed-by: Tom Stellard t...@stellard.net
Do you have commit access yet?
-Tom
---
lib/Target
On Fri, Aug 09, 2013 at 07:54:11AM +0200, Michel Dänzer wrote:
On Don, 2013-08-08 at 11:32 -0700, Tom Stellard wrote:
On Thu, Aug 08, 2013 at 05:36:09PM +0200, Michel Dänzer wrote:
On Don, 2013-08-08 at 08:00 -0700, Tom Stellard wrote:
On Thu, Aug 08, 2013 at 02:20:54AM +0200, Marek
On Fri, Aug 09, 2013 at 07:35:02AM -0700, Tom Stellard wrote:
On Fri, Aug 09, 2013 at 07:54:11AM +0200, Michel Dänzer wrote:
On Don, 2013-08-08 at 11:32 -0700, Tom Stellard wrote:
On Thu, Aug 08, 2013 at 05:36:09PM +0200, Michel Dänzer wrote:
On Don, 2013-08-08 at 08:00 -0700, Tom
On Fri, Aug 09, 2013 at 02:59:07PM +0200, Niels Ole Salscheider wrote:
---
This series is:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Your implementation of SITargetLowering::isFMAFasterThanFMulAndFAdd()
is correct for SI, not sure about Sea Islands, but we can always fix it
later
On Thu, Aug 08, 2013 at 01:51:39PM +0200, Marek Olšák wrote:
Interleaving might not be a good idea, but they could be in the same
array, like this:
0..15: textures
16..31: FMASK textures
I'll test LLVM master, but we should probably bump the LLVM version
requirement in configure.ac to
On Thu, Aug 08, 2013 at 02:20:54AM +0200, Marek Olšák wrote:
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 7 ++--
src/gallium/drivers/radeonsi/radeonsi_shader.h | 58
++
src/gallium/drivers/radeonsi/si_state_draw.c | 1 +
3 files changed, 36
On Thu, Aug 08, 2013 at 02:20:54AM +0200, Marek Olšák wrote:
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 7 ++--
src/gallium/drivers/radeonsi/radeonsi_shader.h | 58
++
src/gallium/drivers/radeonsi/si_state_draw.c | 1 +
3 files changed, 36
On Thu, Aug 08, 2013 at 05:36:09PM +0200, Michel Dänzer wrote:
On Don, 2013-08-08 at 08:00 -0700, Tom Stellard wrote:
On Thu, Aug 08, 2013 at 02:20:54AM +0200, Marek Olšák wrote:
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote:
We should set a goal for the 9.3 release: all drivers should just
build and 'make check' without having to add a bunch of magic
incantations to the configure line. We also need a build bot that
will build and 'make check' every
are:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Please request commit access from Chris, so you can commit these:
http://llvm.org/docs/DeveloperPolicy.html#obtaining-commit-access
Here are instructions for setting up git-svn:
http://llvm.org/docs/GettingStarted.html#for-developers-to-work-with-git
On Wed, Aug 07, 2013 at 03:25:48PM -0700, Ian Romanick wrote:
On 08/07/2013 01:33 PM, Ian Romanick wrote:
On 08/07/2013 08:43 AM, Tom Stellard wrote:
On Tue, Aug 06, 2013 at 10:12:19AM -0700, Ian Romanick wrote:
We should set a goal for the 9.3 release: all drivers should just
build
On Tue, Aug 06, 2013 at 12:26:51PM +0200, Michel Dänzer wrote:
On Mon, 2013-08-05 at 14:58 -0400, Tom Stellard wrote:
From: Tom Stellard thomas.stell...@amd.com
The TGSI-LLVM pass for radeonsi preloads constants and relies on LLVM's
sinking pass to reduce SGPR usage by lowering constant
On Wed, Aug 07, 2013 at 12:05:25AM +0200, Laurent Carlier wrote:
Since llvm -3.4svn r187618, TargetOptions doesn't provide
anymore RealignStack, so only enable it with llvm3.4
Thanks, I've committed this patch.
To the llvmpipe developers: You must now specify the RealignStack option
using
Hi,
The attached patches teach the SI backend to lower BUILD_VECTOR to
REG_SEQUENCE, which should help the register allocator produce better
code. This also fixes 364 array indexing piglit tests.
-Tom
From 90dfb000600eae7a03f3f36fafcfaee1edde5613 Mon Sep 17 00:00:00 2001
From: Tom Stellard
From: Tom Stellard thomas.stell...@amd.com
The TGSI-LLVM pass for radeonsi preloads constants and relies on LLVM's
sinking pass to reduce SGPR usage by lowering constant reads to an
optimal place in the code. However, LLVM's machine sink pass will not
lower instructions that have been selected
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 29 ++
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index
On Wed, Jul 31, 2013 at 01:04:01PM +0200, Michel Dänzer wrote:
LLVM revision 187139 ('Allocate local registers in order for optimal
coloring.') broke some derivative related piglit tests with the radeonsi
driver.
I'm attaching a diff between the bad and good generated code (as printed
On Tue, Jul 30, 2013 at 03:45:13AM +0200, Marek Olšák wrote:
This fixes the F2U opcode for the Mesa driver.
Signed-off-by: Marek Olšák marek.ol...@amd.com
Hi Marek,
You will need to include a lit test with this patch. lit tests are
located in test/CodeGen/R600. You can reuse the existing
, address_spaces);
}
}
--
1.8.3.3
On 2013-07-24 03:58, Francisco Jerez wrote:
Tom Stellard t...@stellard.net writes:
On Mon, Jul 22, 2013 at 09:24:12AM -0400, Jonathan Charest wrote:
To have non-static buffers in local memory, it is necessary to pass them
as arguments to the kernel
On Tue, Jul 30, 2013 at 05:54:58PM +0200, Michel Dänzer wrote:
On Die, 2013-07-30 at 07:47 -0700, Tom Stellard wrote:
You will need to include a lit test with this patch.
Ah yes, this occurred to me after my review. :)
Also, if you try to run piglit with a debug version of LLVM
Hi,
The attached patches add support for 64-bit loads and stores as well as
64-bit kernel arguments.
-Tom
From c4c7d934e951e73f72d998a9f1af0a523d83bbed Mon Sep 17 00:00:00 2001
From: Tom Stellard thomas.stell...@amd.com
Date: Tue, 23 Jul 2013 07:52:50 -0700
Subject: [PATCH 1/2] R600: Use 64-bit
On 2013-07-24 03:58, Francisco Jerez wrote:
Tom Stellard t...@stellard.net writes:
On Mon, Jul 22, 2013 at 09:24:12AM -0400, Jonathan Charest wrote:
To have non-static buffers in local memory, it is necessary to pass them
as arguments to the kernel. This was almost supported
On Tue, Jul 02, 2013 at 10:44:37AM +0200, Niels Ole Salscheider wrote:
Pass cl_khr_fp64 preprocessor definition to clang
Pushed, thanks.
-Tom
Signed-off-by: Niels Ole Salscheider niels_...@salscheider-online.de
---
src/gallium/state_trackers/clover/llvm/invocation.cpp | 1 +
1 Datei
in the right direction).
---
.../state_trackers/clover/llvm/invocation.cpp | 31
++
Reviewed-by: Tom Stellard thomas.stell...@amd.com
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium
reported by the
compiler.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
On Sun, Jul 21, 2013 at 07:46:36PM +0200, Francisco Jerez wrote:
Tom Stellard t...@stellard.net writes:
Hi,
This series improves clover's kernel argument handling by allowing drivers
to
specify an alignment for the input buffer and also by sign/zero extending
the
arguments when
On Fri, Jul 19, 2013 at 10:42:42AM -0700, Kenneth Graunke wrote:
On 07/10/2013 04:38 PM, Ian Romanick wrote:
[snip]
Could we just change our Mark the patch with 'NOTE: ...' policy with
To have the patch automatically included in the stable tree, add the tag
Cc:
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/SIISelLowering.cpp | 15 +++
lib/Target/R600/SIISelLowering.h | 1 +
test/CodeGen/R600/zero_extend.ll | 18 ++
3 files changed, 34 insertions(+)
create mode 100644 test/CodeGen/R600/zero_extend.ll
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 29 ++
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index
From: Tom Stellard thomas.stell...@amd.com
The TGSI-LLVM pass for radeonsi preloads constants and relies on LLVM's
sinking pass to reduce SGPR usage by lowering constant reads to an
optimal place in the code. However, LLVM's machine sink pass will not
lower instructions that have been selected
extension of boolean to 32-bit ints,
I'd say that we should open a new bug for that.
Sounds good to me.
-Tom
On Tue, Jul 16, 2013 at 8:39 PM, Tom Stellard t...@stellard.net wrote:
Hi,
The attached three patches along with this one should fix VSELECT on SI
as well.
-Tom
On Tue, Jul
On Tue, Jul 16, 2013 at 07:03:29AM -0700, Jose Fonseca wrote:
- Original Message -
Has anyone had a chance to look at this series?
No, I just noticed this one now.
FWIW, I don't see much value in constifying gallium interfaces:
- interfaces like pipe_screen have no state
On Wed, Jul 17, 2013 at 10:25:31AM -0500, Aaron Watry wrote:
On Tue, Jul 9, 2013 at 11:21 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
v2:
- Extend to target size rather than aligned size
- Support for big-endian
---
src/gallium
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/AMDGPUISelLowering.cpp | 3 +++
lib/Target/R600/R600ISelLowering.cpp | 3 ---
test/CodeGen/R600/vselect.ll | 30 ++
3 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/lib/Target
From: Tom Stellard thomas.stell...@amd.com
These are really the same address space in hardware. The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access. When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addresing
https://bugs.freedesktop.org/show_bug.cgi?id=66175). Once SETCC is
fixed for SI, we should probably add SI-CHECK lines to vselect.ll
--Aaron
On Tue, Jul 16, 2013 at 2:15 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600
, because an application won't be able to
use those functions unless it explicitly enables fp64 support with :
#pragma OPENCL EXTENSION cl_khr_fp64 : enable
since clang will generate an error if you use doubles types without
enabling the extension.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Hi Jonathan,
Sorry for the delay. I've pushed this patch, thanks!
-Tom
On Wed, Jul 03, 2013 at 11:05:43AM +1000, Jonathan Liu wrote:
Bump.
On 4 June 2013 23:04, Jonathan Liu net...@gmail.com wrote:
The AC_CHECK_FILE macro can't be used for cross compiling as it will
result in error:
On Thu, Jun 27, 2013 at 11:13:37PM +0200, Klemens Baum wrote:
Pushed, thanks for the patch! Sorry for the delay.
-Tom
---
configure.ac | 41 ++---
1 file changed, 26 insertions(+), 15 deletions(-)
diff --git a/configure.ac b/configure.ac
index
On Wed, Jul 10, 2013 at 12:32:25PM +0200, Michel Dänzer wrote:
On Fre, 2013-06-28 at 14:37 -0700, Tom Stellard wrote:
On Wed, Jun 19, 2013 at 06:28:21PM +0200, Michel Dänzer wrote:
These patches implement enough of local memory support to allow radeonsi
to use that for computing
From: Tom Stellard thomas.stell...@amd.com
Query the driver using PIPE_CAP_ENDIANNESS rather than always returning
true.
---
src/gallium/state_trackers/clover/api/device.cpp | 3 ++-
src/gallium/state_trackers/clover/core/device.cpp | 5 +
src/gallium/state_trackers/clover/core/device.hpp
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/core/kernel.cpp | 40 +++
src/gallium/state_trackers/clover/core/kernel.hpp | 10 +++---
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/docs/source/screen.rst | 2 ++
src/gallium/drivers/freedreno/freedreno_screen.c | 3 +++
src/gallium/drivers/i915/i915_screen.c | 2 ++
src/gallium/drivers/ilo/ilo_screen.c | 2 ++
src/gallium/drivers
From: Tom Stellard thomas.stell...@amd.com
This value for this CAP is the alignment to use when storing kernel
arguments in the input buffer.
v2:
- Allow per-type alignments
---
src/gallium/docs/source/screen.rst| 17 +
src/gallium/drivers/r600/r600_pipe.c
From: Tom Stellard thomas.stell...@amd.com
v2:
- Use a 'pad' argument to align arguments to the correct size.
---
.../state_trackers/clover/core/compiler.hpp| 3 +-
src/gallium/state_trackers/clover/core/kernel.cpp | 16 ++-
src/gallium/state_trackers/clover/core/kernel.hpp | 3
From: Tom Stellard thomas.stell...@amd.com
v2:
- Extend to target size rather than aligned size
- Support for big-endian
---
src/gallium/state_trackers/clover/core/kernel.cpp | 58 --
src/gallium/state_trackers/clover/core/kernel.hpp | 17 ---
src/gallium
On Tue, Jul 02, 2013 at 01:02:06PM -0700, Ian Romanick wrote:
To keep our six-month release cadence, it looks like we'll target
August 22nd for 9.2. That means we'll probably need to make the
release branch on July 18th... that's just over two weeks from now.
Assuming that works for
On Tue, Jul 02, 2013 at 10:44:10AM +0200, Niels Ole Salscheider wrote:
Hi,
the attached patches add initial support for double precision operations on
Southern Islands cards.
Some expressions containing multiple double precision kernel arguments cause
llvm to run until all memory is
On Fri, Jun 28, 2013 at 03:05:04PM -0400, alexdeuc...@gmail.com wrote:
From: Alex Deucher alexander.deuc...@amd.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Committed, thanks!
-Tom
---
lib/Target/R600/Processors.td |3 +++
1 files changed, 3 insertions(+), 0
it still fails because it tries to copy a VGPR to
an SGPR, which is not possible.
Can you add some lit tests for these new intrinsics and also add CHECK
lines for SI to the existing local-memory.ll test.
With the tests added, these patches are:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r300/Makefile.am |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r300/Makefile.am
b/src/gallium/drivers/r300/Makefile.am
index 49264c4..f82b8e9 100644
--- a/src/gallium/drivers/r300
From: Tom Stellard thomas.stell...@amd.com
https://bugs.freedesktop.org/show_bug.cgi?id=63520
NOTE: This is a candidate for the stable branches.
---
src/gallium/drivers/r300/Makefile.am |1 +
.../drivers/r300/compiler/radeon_pair_regalloc.c |8 ++
.../r300/compiler/tests
From: Tom Stellard thomas.stell...@amd.com
The assembly parser can be used to load r300 assembly dumps
and run them through any of the r300 compiler passes.
---
.../r300/compiler/tests/omod_two_writers.test |5 +
.../r300/compiler/tests/r300_compiler_tests.h |1 +
.../tests
Thanks Vinson, I've pushed this. Sorry for the delay.
-Tom
On Tue, Jun 25, 2013 at 09:37:07PM -0700, Vinson Lee wrote:
Fixes Resource leak defect reported by Coverity.
Signed-off-by: Vinson Lee v...@freedesktop.org
---
src/gallium/drivers/radeonsi/radeonsi_compute.c | 1 +
1 file
From: Chih-Wei Huang cwhu...@android-x86.org
Add the sb CXX files to the Android Makefile and also stop using some
c++11 features.
---
src/gallium/drivers/r600/Android.mk | 5 +++--
src/gallium/drivers/r600/sb/sb_bc.h | 4 ++--
src/gallium/drivers/r600/sb/sb_ra_init.cpp | 2 +-
that much code ; R600Packetizer is called after
cube/reduction op are lowered
by R600Expand pass and thus the isVector/ReductionOp check is useless. I may
have left some debug code in
isSoloInstruction code though.
- Mail original -
De : Tom Stellard t...@stellard.net
À : llvm
Hi,
This series improves clover's kernel argument handling by allowing drivers to
specify an alignment for the input buffer and also by sign/zero extending the
arguments when required. In order to test these patches on r600g and radeonsi,
you will need to also apply the LLVM patches which were
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/core/kernel.cpp | 40 +++
src/gallium/state_trackers/clover/core/kernel.hpp | 10 +++---
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core
From: Tom Stellard thomas.stell...@amd.com
This value for this CAP is the alignment to use when storing kernel
arguments in the input buffer.
---
src/gallium/docs/source/screen.rst| 13 +
src/gallium/drivers/r600/r600_pipe.c | 11 ++-
src/gallium
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/core/kernel.cpp | 28 +--
src/gallium/state_trackers/clover/core/kernel.hpp | 5
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/core/kernel.cpp | 23 +++---
src/gallium/state_trackers/clover/core/kernel.hpp | 4 +++-
src/gallium/state_trackers/clover/core/module.hpp | 10 +-
.../state_trackers/clover/llvm
and commit.
Tested-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index
On Sun, Jun 23, 2013 at 05:56:15PM -0400, Alex Deucher wrote:
On Sun, Jun 23, 2013 at 2:24 PM, Marek Olšák mar...@gmail.com wrote:
Hi Alex,
rctx-framebuffer.state.nr_cbufs might not contain what you think it
does, because the framebuffer that needs flushing may have been
replaced by a
On Thu, Jun 20, 2013 at 06:43:49PM -0500, Aaron Watry wrote:
Note: Only adding test for evergreen, not SI yet.
When I attempted to expand vselect for SI, I got the following:
llc:
/home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522:
llvm::SDValue
that in the
individual targets.
Signed-off-by: Aaron Watry awa...@gmail.com
Just one small comment on the SHL patch, but with that fixed these
patches are:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
R600/SI: Expand and of v2i32/v4i32 for SI
R600/SI: Expand mul of v2i32/v4i32 for SI
R600
On Fri, Jun 21, 2013 at 09:44:29AM -0500, Aaron Watry wrote:
Add some constant load v2i32/v4i32 tests for both EG and SI.
Tested on: Pitcairn (7850) and Cedar (54xx)
Signed-off-by: Aaron Watry awa...@gmail.com
---
lib/Target/R600/R600Instructions.td | 3 +++
On Wed, May 08, 2013 at 06:19:11PM -0500, Aaron Watry wrote:
Signed-off-by: Aaron Watry awa...@gmail.com
I'm afraid I overlooked this patch, sorry.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/R600ISelLowering.cpp |2 ++
test/CodeGen/R600/sub.ll
On Wed, Jun 19, 2013 at 08:51:01AM -0700, Tom Stellard wrote:
On Mon, Jun 17, 2013 at 04:11:38PM -0500, Aaron Watry wrote:
The custom lowering causes llc to crash with a segfault.
Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without
On Tue, Jun 18, 2013 at 08:26:53PM -0500, Aaron Watry wrote:
Tested on Pitcairn by: Aaron Watry awa...@gmail.com
Thanks.
Follow-up question: Would it be as easy as it looks to add v2i32 right away?
I think so.
-Tom
On Tue, Jun 18, 2013 at 6:21 PM, Tom Stellard t...@stellard.net wrote
On Mon, Jun 17, 2013 at 04:11:38PM -0500, Aaron Watry wrote:
The custom lowering causes llc to crash with a segfault.
Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.
Signed-off-by: Aaron Watryawa...@gmail.com
---
On Mon, Jun 17, 2013 at 04:11:39PM -0500, Aaron Watry wrote:
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Signed-off-by: Aaron Watry awa...@gmail.com
---
lib/Target/R600/SIISelLowering.cpp | 2 ++
test/CodeGen
the current R600 back-end
emits the operation order.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Signed-off-by: Aaron Watryawa...@gmail.com
---
lib/Target/R600/SIISelLowering.cpp | 3 +++
test/CodeGen/R600/sub.ll | 37 +++--
2 files changed, 34
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/R600Instructions.td | 9 +
test/CodeGen/R600/load.ll | 1 +
2 files changed, 10 insertions(+)
diff --git a/lib/Target/R600/R600Instructions.td
b/lib/Target/R600/R600Instructions.td
index 83d735f..803f597 100644
From: Tom Stellard thomas.stell...@amd.com
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space. Allowing
unaligned loads/stores for 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple
From: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/AMDGPUCallingConv.td| 9 +
test/CodeGen/R600/128bit-kernel-args.ll | 16 ++--
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/lib/Target/R600/AMDGPUCallingConv.td
b/lib/Target/R600
=64257
The other patch fix a typo that causes instructions not to use PV/PS register
when R600Packetizers evaluates read port limitations.
It prevents some bundling opportunities in some (not so frequent) situation.
Vincent
Both patches are Reviewed-by: Tom Stellard thomas.stell...@amd.com
From: Tom Stellard thomas.stell...@amd.com
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):
Before:
1173
On Thu, Jun 06, 2013 at 10:29:21AM -0500, Aaron Watry wrote:
Looks good to me. Is there a piglit test for this?
I just sent a test for this to the list.
-Tom
--Aaron
On Wed, Jun 5, 2013 at 7:12 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
On Fri, Jun 14, 2013 at 08:40:38AM -0500, Aaron Watry wrote:
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.
Pushed, thanks!
-Tom
Signed-off-by: Aaron Watry awa...@gmail.com
---
On Wed, Jun 12, 2013 at 06:37:39PM -0700, Matt Arsenault wrote:
On 06/12/2013 05:42 PM, Tom Stellard wrote:
Hi,
The attached patches add support for local address space on
Evergreen / Northern Islands GPUs.
Please Review.
-Tom
+ def int_AMDGPU_barrier_local : Intrinsic
On Thu, Jun 13, 2013 at 05:51:49PM -0500, Aaron Watry wrote:
On Wed, Jun 12, 2013 at 7:34 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c | 23 +++-
src/gallium/drivers/r600
From: Tom Stellard thomas.stell...@amd.com
---
r600/lib/SOURCES | 2 ++
r600/lib/synchronization/barrier.cl | 15 +++
r600/lib/synchronization/barrier_impl.ll | 12
3 files changed, 29 insertions(+)
create mode 100644 r600/lib
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c | 23 +++-
src/gallium/drivers/r600/r600_shader.c | 32
2 files changed, 22 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/r600
From: Tom Stellard thomas.stell...@amd.com
And allocate the correct amount before dispatching the kernel.
---
src/gallium/drivers/r600/evergreen_compute.c | 53 +++---
.../drivers/r600/evergreen_compute_internal.h | 1 +
src/gallium/drivers/r600/evergreen_state.c
...@amd.com
Thanks for doing this.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon
On Fri, Jun 07, 2013 at 05:48:05PM -0700, Tom Stellard wrote:
On Fri, Jun 07, 2013 at 05:24:42PM +0200, Michel Dänzer wrote:
The most important difference to the previous version of these is that
whole quad mode is now enabled and M0 initialized appropriately for the
LDS instructions
.
For the series:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
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On Fri, Jun 07, 2013 at 05:24:42PM +0200, Michel Dänzer wrote:
The most important difference to the previous version of these is that
whole quad mode is now enabled and M0 initialized appropriately for the
LDS instructions, which now allows all of the relevant piglit tests to
pass.
Hi
On Tue, Jun 04, 2013 at 12:46:02AM +0200, Grigori Goronzy wrote:
According to ISA docs, the range is 1..64, so effectively
bytes_to_fetch-1.
As far as I can tell this patch is correct, though I'm not sure what impact
this really has on the shader.
Reviewed-by: Tom Stellard thomas.stell
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/llvm/invocation.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index 2d115ed..8ec089d
On Mon, May 27, 2013 at 02:15:21AM +0400, Vadim Girlin wrote:
This will help to improve dumps of the compute shaders,
also it will be required for complete handling of RAT instructions in sb.
Signed-off-by: Vadim Girlin vadimgir...@gmail.com
---
src/gallium/drivers/r600/r600_isa.c | 19
On Tue, May 28, 2013 at 12:21:20PM +0200, Michel Dänzer wrote:
On Die, 2013-05-28 at 04:16 +0200, Andreas Hartmetz wrote:
---
configure.ac | 1 +
1 file changed, 1 insertion(+)
diff --git a/configure.ac b/configure.ac
index eef4327..486a4e9 100644
--- a/configure.ac
+++
On Tue, May 28, 2013 at 11:59:41PM +0200, Andreas Hartmetz wrote:
r600g needs it too, so add ipo in the common radeon_llvm_check().
radeonsi compiled and linked, but it failed at dynamic link time
with a missing symbol.
Pushed, thanks!
-Tom
---
configure.ac | 4 ++--
1 file changed, 2
Hi,
These patches along with the associated LLVM changes improve compute
support on radeonsi to the point were it can run a number of simple apps,
including the bitcoin mining program bfgminer.
Patch #4 re-introduces the r600_upload_const_buffer() function that was removed
in
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index b988e72..7a79db3 100644
--- a/src
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_compute.c | 31 +++--
1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_compute.c
b/src/gallium/drivers/radeonsi/radeonsi_compute.c
index
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/radeonsi/r600_buffer.c | 31 +
src/gallium/drivers/radeonsi/radeonsi_compute.c | 26 ++---
src/gallium/drivers/radeonsi/si_state.c | 29 +++
3 files changed
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