Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

2017-05-02 Thread Francisco Jerez
Samuel Iglesias Gonsálvez writes: > On Mon, 2017-05-01 at 14:55 +0200, Samuel Iglesias Gonsálvez wrote: >> El Viernes, 28 de abril de 2017 16:27:56 Francisco Jerez escribió: >> > Samuel Iglesias Gonsálvez writes: >> > > On gen7, the swizzles used in

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

2017-05-02 Thread Samuel Iglesias Gonsálvez
On Mon, 2017-05-01 at 14:55 +0200, Samuel Iglesias Gonsálvez wrote: > El Viernes, 28 de abril de 2017 16:27:56 Francisco Jerez escribió: > > Samuel Iglesias Gonsálvez writes: > > > On gen7, the swizzles used in DF align16 instructions works for > > > element > > > size of 32

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

2017-05-01 Thread Samuel Iglesias Gonsálvez
El Viernes, 28 de abril de 2017 16:27:56 Francisco Jerez escribió: > Samuel Iglesias Gonsálvez writes: > > On gen7, the swizzles used in DF align16 instructions works for element > > size of 32 bits, so we can address only 2 consecutive DFs. As we assumed > > that in the

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/3] i965/vec4: fix register width for DF VGRF and UNIFORM

2017-04-28 Thread Francisco Jerez
Samuel Iglesias Gonsálvez writes: > On gen7, the swizzles used in DF align16 instructions works for element > size of 32 bits, so we can address only 2 consecutive DFs. As we assumed that > in the rest of the code and prepare the instructions for this > (scalarize_df()), >