Quoting Kenneth Graunke (2017-08-02 02:14:22)
> The cacheline alignment restriction is on the base address; the pitch
> can be anything.
From my understanding of the bug, this is correct and the workaround is
to adjust the xoffset as you have done. (And since the chunk is limited
to less than 32k
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch %
