Re: [Mesa-dev] [PATCH] i965: Require pixel alignment for GPU copy blit

2014-09-23 Thread Cody Northrop
Thanks, Neil. Yeah, I had the same thoughts regarding whether it is a valid offset. The trace does render correctly on Nvidia proprietary driver, but renders even worse on Intel Windows driver (blank white screen after the bubbles pass). I believe it used to render correctly on Windows, but maybe

Re: [Mesa-dev] [PATCH] i965: Require pixel alignment for GPU copy blit

2014-09-23 Thread Neil Roberts
I just noticed this wording in the GL spec regarding buffer objects: “Clients must align data elements consistent with the requirements of the client platform, with an additional base-level requirement that an offset within a buffer to a datum comprising N basic machine units be a multiple of N.”

Re: [Mesa-dev] [PATCH] i965: Require pixel alignment for GPU copy blit

2014-09-23 Thread Neil Roberts
This patch looks good to me. The wording in the bspec seems a little vague so I was wondering if maybe the real restriction is that the offset must be 4-byte aligned rather than being aligned to the bpp. However I tried it with a 16-bit type and sure enough it works to have an offset aligned to tw

[Mesa-dev] [PATCH] i965: Require pixel alignment for GPU copy blit

2014-09-15 Thread Cody Northrop
The blitter will start at a pixel's natural alignment. For PBOs, if the provided offset if not aligned, bits will get dropped. This change adds offset alignment check for src and dst, kicking back if the requirements are not met. The change is based on following verbiage from BSPEC: Color pixel