Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

2016-03-19 Thread Pierre Moreau
On 06:24 PM - Mar 19 2016, Ilia Mirkin wrote: > On Sat, Mar 19, 2016 at 6:15 PM, Pierre Moreau wrote: > > On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: > >> Not 100% sure, but pretty sure this is wrong. Can you provide the > >> generated sequence of instructions in response

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

2016-03-19 Thread Ilia Mirkin
On Sat, Mar 19, 2016 at 6:15 PM, Pierre Moreau wrote: > On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: >> Not 100% sure, but pretty sure this is wrong. Can you provide the >> generated sequence of instructions in response to a 64-bit mul and >> mad? > > For the given mul: >

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

2016-03-19 Thread Pierre Moreau
On 06:05 PM - Mar 19 2016, Ilia Mirkin wrote: > Not 100% sure, but pretty sure this is wrong. Can you provide the > generated sequence of instructions in response to a 64-bit mul and > mad? For the given mul: mov u64 %r42d 0x0004 mov u64 %r52d 0x0002 mul u64 %r55d

Re: [Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

2016-03-19 Thread Ilia Mirkin
Not 100% sure, but pretty sure this is wrong. Can you provide the generated sequence of instructions in response to a 64-bit mul and mad? On Sat, Mar 19, 2016 at 5:56 PM, Pierre Moreau wrote: > Two 32-bit MAD or MUL operations are generated in place of the original 64-bit

[Mesa-dev] [PATCH] nv50/ir: Split 64-bit MAD and MUL operations

2016-03-19 Thread Pierre Moreau
Two 32-bit MAD or MUL operations are generated in place of the original 64-bit operation. All operands can either be signed or unsigned, but they have to be integers. Signed-off-by: Pierre Moreau --- src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp | 11