On 09.09.2017 13:26, Bas Nieuwenhuizen wrote:
Out of curiosity, don't SI and CIK also support the out of order bits?
Why only enable it on VI?
According to internal docs, there's a lock-up bug on older chips.
(and would enabling it on 1 SE chips hurt anything?)
I don't think so, except for
Out of curiosity, don't SI and CIK also support the out of order bits?
Why only enable it on VI?
(and would enabling it on 1 SE chips hurt anything?)
On Sat, Sep 9, 2017 at 12:43 PM, Nicolai Hähnle wrote:
> Hi all,
>
> This is my attempt at restructuring the logic for out-of-order
> rasterizatio
Hi all,
This is my attempt at restructuring the logic for out-of-order
rasterization, including commutative blending cases. Tested on
Tonga and Polaris so far.
The series adds some new options:
R600_DEBUG=nooutoforder --> disable entirely
drirc options:
radeonsi_assume_no_z_fights --> as the n
