Re: [Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

On Thu, 2017-06-22 at 17:02 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez writes: > > > Hello, > > > > As mentioned in the patch series that implemented Ivybridge support > > ARB_gpu_shader_fp64 [0], the only missing feature in that series > > was > > register

Re: [Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

Samuel Iglesias Gonsálvez writes: > Hello, > > As mentioned in the patch series that implemented Ivybridge support > ARB_gpu_shader_fp64 [0], the only missing feature in that series was > register spilling of 64-bit data and, because of that, about ~39 fp64 > piglit tests

Re: [Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

On Thu, 2017-06-15 at 13:15 +0200, Samuel Iglesias Gonsálvez wrote: > Hello, > > As mentioned in the patch series that implemented Ivybridge support > ARB_gpu_shader_fp64 [0], the only missing feature in that series was > register spilling of 64-bit data and, because of that, about ~39 fp64 >

[Mesa-dev] [PATCH 0/6] i965/vec4: Implement partial DF register spilling

Hello, As mentioned in the patch series that implemented Ivybridge support ARB_gpu_shader_fp64 [0], the only missing feature in that series was register spilling of 64-bit data and, because of that, about ~39 fp64 piglit tests failed to spill registers. This new patch series implement register