Re: [Mesa-dev] [PATCH 03/11] i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

2014-08-10 Thread Kenneth Graunke
On Sunday, August 10, 2014 04:34:36 PM Chris Forbes wrote: + if (align16) { + /* Emulate the Gen7 zeroing bug (see comments in vec4_visitor's + * emit_pack_half_2x16 method.) + */ + brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)); +

[Mesa-dev] [PATCH 03/11] i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

2014-08-09 Thread Kenneth Graunke
When we combine the Gen4-7 and Gen8+ generators, we'll need to handle half float packing/unpacking functions somehow. The Gen8+ generator code today just emulates the behavior of the Gen7 F32TO16/F16TO32 instructions, including the align16 mode bugs. Rather than messing with

Re: [Mesa-dev] [PATCH 03/11] i965/eu: Emulate F32TO16 and F16TO32 on Broadwell.

2014-08-09 Thread Chris Forbes
+ if (align16) { + /* Emulate the Gen7 zeroing bug (see comments in vec4_visitor's + * emit_pack_half_2x16 method.) + */ + brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u)); + } + return brw_MOV(p, retype(dst,