On 02/19/2014 01:32 PM, Anuj Phogat wrote:
> On Wed, Feb 19, 2014 at 2:04 AM, Kenneth Graunke
> wrote:
>> This is a straight port from gen7_wm_state.c; I haven't looked into
>> whether we can do both.
>>
> Verified that restriction still holds true in BDW.
> See 3D Pipeline Stages > Pixel > Pixel
On Wed, Feb 19, 2014 at 2:04 AM, Kenneth Graunke wrote:
> This is a straight port from gen7_wm_state.c; I haven't looked into
> whether we can do both.
>
Verified that restriction still holds true in BDW.
See 3D Pipeline Stages > Pixel > Pixel Shader Thread Generation >
Pixel Grouping (Dispatch Si
Kenneth Graunke writes:
> This is a straight port from gen7_wm_state.c; I haven't looked into
> whether we can do both.
>
> v2: Actually do it right.
>
> Signed-off-by: Kenneth Graunke
> @@ -205,13 +201,39 @@ upload_ps_state(struct brw_context *brw)
> else
>dw6 |= GEN7_PS_POSOFFSET_
This is a straight port from gen7_wm_state.c; I haven't looked into
whether we can do both.
v2: Actually do it right.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen8_ps_state.c | 38 ---
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a
