From: Marek Olšák <marek.ol...@amd.com> This is based on our docs (recently updated), not amdvlk. --- .../drivers/radeonsi/si_state_binning.c | 73 ++++++++++--------- 1 file changed, 38 insertions(+), 35 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c
b/src/gallium/drivers/radeonsi/si_state_binning.c
index 895374e4f42..c49f7c7177f 100644
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -30,21 +30,21 @@
struct uvec2 {
unsigned x, y;
};
struct si_bin_size_map {
unsigned start;
unsigned bin_size_x;
unsigned bin_size_y;
};
-typedef struct si_bin_size_map si_bin_size_subtable[3][9];
+typedef struct si_bin_size_map si_bin_size_subtable[3][10];
/* Find the bin size where sum is >= table[i].start and < table[i + 1].start.
*/
static struct uvec2 si_find_bin_size(struct si_screen *sscreen,
const si_bin_size_subtable table[],
unsigned sum)
{
unsigned log_num_rb_per_se =
util_logbase2_ceil(sscreen->info.num_render_backends /
sscreen->info.max_se);
unsigned log_num_se = util_logbase2_ceil(sscreen->info.max_se);
@@ -117,21 +117,21 @@ static struct uvec2 si_get_color_bin_size(struct
si_context *sctx,
{ UINT_MAX, 0, 0 },
},
},
{
/* Two RB / SE */
{
/* One shader engine */
{ 0, 128, 128 },
{ 2, 64, 128 },
{ 3, 32, 128 },
- { 5, 16, 128 },
+ { 9, 16, 128 },
{ 33, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
/* Two shader engines */
{ 0, 128, 128 },
{ 3, 64, 128 },
{ 5, 32, 128 },
{ 9, 16, 128 },
{ 33, 0, 0 },
@@ -150,42 +150,42 @@ static struct uvec2 si_get_color_bin_size(struct
si_context *sctx,
},
{
/* Four RB / SE */
{
/* One shader engine */
{ 0, 128, 256 },
{ 2, 128, 128 },
{ 3, 64, 128 },
{ 5, 32, 128 },
{ 9, 16, 128 },
- { 33, 0, 0 },
+ { 17, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
/* Two shader engines */
{ 0, 256, 256 },
{ 2, 128, 256 },
{ 3, 128, 128 },
{ 5, 64, 128 },
{ 9, 32, 128 },
{ 17, 16, 128 },
{ 33, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
/* Four shader engines */
{ 0, 256, 512 },
- { 2, 256, 256 },
- { 3, 128, 256 },
- { 5, 128, 128 },
- { 9, 64, 128 },
- { 17, 16, 128 },
+ { 2, 128, 512 },
+ { 3, 64, 512 },
+ { 5, 32, 512 },
+ { 9, 32, 256 },
+ { 17, 32, 128 },
{ 33, 0, 0 },
{ UINT_MAX, 0, 0 },
},
},
};
return si_find_bin_size(sctx->screen, table, sum);
}
static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
@@ -205,123 +205,126 @@ static struct uvec2 si_get_depth_bin_size(struct
si_context *sctx)
unsigned stencil_coeff = rtex->surface.has_stencil &&
dsa->stencil_enabled ? 1 : 0;
unsigned sum = 4 * (depth_coeff + stencil_coeff) *
rtex->buffer.b.b.nr_samples;
static const si_bin_size_subtable table[] = {
{
// One RB / SE
{
// One shader engine
- { 0, 128, 256 },
- { 2, 128, 128 },
+ { 0, 64, 512 },
+ { 2, 64, 256 },
{ 4, 64, 128 },
{ 7, 32, 128 },
{ 13, 16, 128 },
{ 49, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Two shader engines
- { 0, 256, 256 },
- { 2, 128, 256 },
- { 4, 128, 128 },
+ { 0, 128, 512 },
+ { 2, 64, 512 },
+ { 4, 64, 256 },
{ 7, 64, 128 },
{ 13, 32, 128 },
{ 25, 16, 128 },
{ 49, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 256, 512 },
- { 2, 256, 256 },
- { 4, 128, 256 },
- { 7, 128, 128 },
+ { 2, 128, 512 },
+ { 4, 64, 512 },
+ { 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 16, 128 },
{ 49, 0, 0 },
{ UINT_MAX, 0, 0 },
},
},
{
// Two RB / SE
{
// One shader engine
- { 0, 256, 256 },
- { 2, 128, 256 },
- { 4, 128, 128 },
+ { 0, 128, 512 },
+ { 2, 64, 512 },
+ { 4, 64, 256 },
{ 7, 64, 128 },
{ 13, 32, 128 },
{ 25, 16, 128 },
{ 97, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Two shader engines
{ 0, 256, 512 },
- { 2, 256, 256 },
- { 4, 128, 256 },
- { 7, 128, 128 },
+ { 2, 128, 512 },
+ { 4, 64, 512 },
+ { 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 32, 128 },
{ 49, 16, 128 },
{ 97, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 512, 512 },
{ 2, 256, 512 },
- { 4, 256, 256 },
- { 7, 128, 256 },
- { 13, 128, 128 },
+ { 4, 128, 512 },
+ { 7, 64, 512 },
+ { 13, 64, 256 },
{ 25, 64, 128 },
{ 49, 16, 128 },
{ 97, 0, 0 },
{ UINT_MAX, 0, 0 },
},
},
{
// Four RB / SE
{
// One shader engine
{ 0, 256, 512 },
- { 2, 256, 256 },
- { 4, 128, 256 },
- { 7, 128, 128 },
+ { 2, 128, 512 },
+ { 4, 64, 512 },
+ { 7, 64, 256 },
{ 13, 64, 128 },
{ 25, 32, 128 },
{ 49, 16, 128 },
+ { 193, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Two shader engines
{ 0, 512, 512 },
{ 2, 256, 512 },
- { 4, 256, 256 },
- { 7, 128, 256 },
- { 13, 128, 128 },
+ { 4, 128, 512 },
+ { 7, 64, 512 },
+ { 13, 64, 256 },
{ 25, 64, 128 },
{ 49, 32, 128 },
{ 97, 16, 128 },
+ { 193, 0, 0 },
{ UINT_MAX, 0, 0 },
},
{
// Four shader engines
{ 0, 512, 512 },
{ 4, 256, 512 },
- { 7, 256, 256 },
- { 13, 128, 256 },
- { 25, 128, 128 },
- { 49, 64, 128 },
+ { 7, 128, 512 },
+ { 13, 64, 512 },
+ { 25, 32, 512 },
+ { 49, 32, 256 },
{ 97, 16, 128 },
+ { 193, 0, 0 },
{ UINT_MAX, 0, 0 },
},
},
};
return si_find_bin_size(sctx->screen, table, sum);
}
static void si_emit_dpbb_disable(struct si_context *sctx)
{
--
2.17.0
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