Re: [Mesa-dev] [PATCH 2/2] nvir/nvc0: Properly lower 64-bit SHL/SHR when the shift is an imm

2017-12-03 Thread Pierre Moreau
On 2017-12-03 — 15:36, Ilia Mirkin wrote: > On Sun, Dec 3, 2017 at 3:28 PM, Pierre Moreau wrote: > > The existing lowering code assumed the shift would not be an immediate > > but did not guard against it. However, in the constant folding pass, a > > multiplication by a

Re: [Mesa-dev] [PATCH 2/2] nvir/nvc0: Properly lower 64-bit SHL/SHR when the shift is an imm

2017-12-03 Thread Ilia Mirkin
On Sun, Dec 3, 2017 at 3:28 PM, Pierre Moreau wrote: > The existing lowering code assumed the shift would not be an immediate > but did not guard against it. However, in the constant folding pass, a > multiplication by a power-of-2 immediate would get optimised into a >

[Mesa-dev] [PATCH 2/2] nvir/nvc0: Properly lower 64-bit SHL/SHR when the shift is an imm

2017-12-03 Thread Pierre Moreau
The existing lowering code assumed the shift would not be an immediate but did not guard against it. However, in the constant folding pass, a multiplication by a power-of-2 immediate would get optimised into a shift-left instruction, with the shift value being an immediate. Signed-off-by: Pierre