On Tue, Sep 3, 2013 at 9:19 PM, Ville Syrjälä
wrote:
> On Thu, Aug 15, 2013 at 10:39:31PM +0200, Vedran Rodic wrote:
>> > We do have the set_caching ioctl. It's enough to flip the PTEs to UC and
>> > let MOCS manage things. I actually did a few experiments on my IVB. I
>> > made all Mesa's buffers
On Thu, Aug 15, 2013 at 10:39:31PM +0200, Vedran Rodic wrote:
> > We do have the set_caching ioctl. It's enough to flip the PTEs to UC and
> > let MOCS manage things. I actually did a few experiments on my IVB. I
> > made all Mesa's buffers UC via PTEs by patching libdrm to change the
> > cache mod
> We do have the set_caching ioctl. It's enough to flip the PTEs to UC and
> let MOCS manage things. I actually did a few experiments on my IVB. I
> made all Mesa's buffers UC via PTEs by patching libdrm to change the
> cache mode of each bo after allocation. Then I fiddled with the MOCS
> LLC bits
On 08/15/2013 09:11 AM, Ville Syrjälä wrote:
On Thu, Aug 15, 2013 at 08:08:12AM -0700, Chad Versace wrote:
I would like such a cache-control ioctl, as long the ioctl can also
be used to change the object's cacheing policy in addition to
setting it at object creation. This would be
needed when
On Thu, Aug 15, 2013 at 08:08:12AM -0700, Chad Versace wrote:
> On 08/14/2013 12:50 AM, Ville Syrjälä wrote:
> > On Wed, Aug 14, 2013 at 10:45:23AM +0300, Ville Syrjälä wrote:
> >> On Tue, Aug 13, 2013 at 05:46:55PM -0700, Chad Versace wrote:
> >>> On 08/13/2013 03:31 PM, Vedran Rodic wrote:
>
On 08/14/2013 12:50 AM, Ville Syrjälä wrote:
On Wed, Aug 14, 2013 at 10:45:23AM +0300, Ville Syrjälä wrote:
On Tue, Aug 13, 2013 at 05:46:55PM -0700, Chad Versace wrote:
On 08/13/2013 03:31 PM, Vedran Rodic wrote:
On Mon, Aug 12, 2013 at 3:07 PM, wrote:
From: Ville Syrjälä
For L3 cache
On Wed, Aug 14, 2013 at 10:45:23AM +0300, Ville Syrjälä wrote:
> On Tue, Aug 13, 2013 at 05:46:55PM -0700, Chad Versace wrote:
> > On 08/13/2013 03:31 PM, Vedran Rodic wrote:
> > > On Mon, Aug 12, 2013 at 3:07 PM, wrote:
> > >> From: Ville Syrjälä
> > >>
> > >> IVB/BYT also has the same L3 cache
On Tue, Aug 13, 2013 at 05:46:55PM -0700, Chad Versace wrote:
> On 08/13/2013 03:31 PM, Vedran Rodic wrote:
> > On Mon, Aug 12, 2013 at 3:07 PM, wrote:
> >> From: Ville Syrjälä
> >>
> >> IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
> >> so let's make use of it.
> >
> > Accor
On 08/12/2013 06:07 AM, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except
On 08/13/2013 03:31 PM, Vedran Rodic wrote:
On Mon, Aug 12, 2013 at 3:07 PM, wrote:
From: Ville Syrjälä
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
According to the discussion we had on #intel-gfx a few weeks ago, on
IVB all Mesa memory is alr
On Mon, Aug 12, 2013 at 3:07 PM, wrote:
> From: Ville Syrjälä
>
> IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
> so let's make use of it.
According to the discussion we had on #intel-gfx a few weeks ago, on
IVB all Mesa memory is already marked as cached in DRM allocated PT
From: Ville Syrjälä
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at han
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