Signed-off-by: Sonny Jiang <sonny.ji...@amd.com>
---
src/gallium/drivers/radeonsi/si_gfx_cs.c | 1 +
src/gallium/drivers/radeonsi/si_state.h | 1 +
.../drivers/radeonsi/si_state_shaders.c | 51 ++++++++++---------
3 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c
b/src/gallium/drivers/radeonsi/si_gfx_cs.c
index 8c1bee8ed6..7cf1f6f4b7 100644
--- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
+++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
@@ -378,6 +378,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] =
0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT]
= 0x00000000;
ctx->tracked_regs.reg_value[SI_TRACKED_CB_SHADER_MASK] =
0xffffffff;
+ ctx->tracked_regs.reg_value[SI_TRACKED_VGT_TF_PARAM] =
0x00000000;
/* Set all saved registers state to saved. */
ctx->tracked_regs.reg_saved = 0xffffffffffffffff;
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 878b67f0ed..54b03e0992 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -312,6 +312,7 @@ enum si_tracked_reg {
SI_TRACKED_SPI_SHADER_COL_FORMAT,
SI_TRACKED_CB_SHADER_MASK,
+ SI_TRACKED_VGT_TF_PARAM,
SI_NUM_TRACKED_REGS,
};
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index e5732f7920..a8d2769475 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -336,9 +336,8 @@ void si_destroy_shader_cache(struct si_screen *sscreen)
/* SHADER STATES */
-static void si_set_tesseval_regs(struct si_screen *sscreen,
- struct si_shader_selector *tes,
- struct si_pm4_state *pm4)
+static void si_set_tesseval_regs(struct si_context *sctx,
+ struct si_shader_selector *tes)
{
struct tgsi_shader_info *info = &tes->info;
unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
@@ -387,20 +386,21 @@ static void si_set_tesseval_regs(struct si_screen
*sscreen,
else
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
- if (sscreen->has_distributed_tess) {
- if (sscreen->info.family == CHIP_FIJI ||
- sscreen->info.family >= CHIP_POLARIS10)
+ if (sctx->screen->has_distributed_tess) {
+ if (sctx->family == CHIP_FIJI ||
+ sctx->family >= CHIP_POLARIS10)
distribution_mode =
V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
} else
distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
- si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
- S_028B6C_TYPE(type) |
- S_028B6C_PARTITIONING(partitioning) |
- S_028B6C_TOPOLOGY(topology) |
- S_028B6C_DISTRIBUTION_MODE(distribution_mode));
+ radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
+ SI_TRACKED_VGT_TF_PARAM,
+ S_028B6C_TYPE(type) |
+ S_028B6C_PARTITIONING(partitioning) |
+ S_028B6C_TOPOLOGY(topology) |
+ S_028B6C_DISTRIBUTION_MODE(distribution_mode));
}
/* Polaris needs different VTX_REUSE_DEPTH settings depending on
@@ -562,10 +562,16 @@ static void si_emit_shader_es(struct si_context *sctx)
{
struct si_shader *shader = sctx->queued.named.es->shader;
- if (shader)
- radeon_opt_set_context_reg(sctx,
R_028AAC_VGT_ESGS_RING_ITEMSIZE,
- SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
- shader->selector->esgs_itemsize / 4);
+ if (!shader)
+ return;
+
+ radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
+ SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
+ shader->selector->esgs_itemsize / 4);
+
+ if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
+ si_set_tesseval_regs(sctx, shader->selector);
+
}
static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
@@ -611,9 +617,6 @@ static void si_shader_es(struct si_screen *sscreen, struct
si_shader *shader)
S_00B32C_OC_LDS_EN(oc_lds_en) |
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
- if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- si_set_tesseval_regs(sscreen, shader->selector, pm4);
-
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
@@ -826,6 +829,9 @@ static void si_emit_shader_gs(struct si_context *sctx)
radeon_opt_set_context_reg(sctx,
R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->key.part.gs.es->esgs_itemsize / 4);
+
+ if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
+ si_set_tesseval_regs(sctx, shader->key.part.gs.es);
}
}
@@ -894,9 +900,6 @@ static void si_shader_gs(struct si_screen *sscreen, struct
si_shader *shader)
S_00B22C_LDS_SIZE(gs_info.lds_size) |
S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
- if (es_type == PIPE_SHADER_TESS_EVAL)
- si_set_tesseval_regs(sscreen, shader->key.part.gs.es,
pm4);
-
polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
NULL, pm4);
} else {
@@ -998,6 +1001,9 @@ static void si_emit_shader_vs(struct si_context *sctx)
S_028818_VPORT_X_SCALE_ENA(1) |
S_028818_VPORT_X_OFFSET_ENA(1) |
S_028818_VPORT_Y_SCALE_ENA(1) |
S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) |
S_028818_VPORT_Z_OFFSET_ENA(1));
+
+ if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
+ si_set_tesseval_regs(sctx, shader->selector);
}
/**
@@ -1067,9 +1073,6 @@ static void si_shader_vs(struct si_screen *sscreen,
struct si_shader *shader,
S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
- if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- si_set_tesseval_regs(sscreen, shader->selector, pm4);
-
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
--
2.17.1
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