Re: [Mesa-dev] [PATCH v2 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

On Mon, 2016-07-11 at 12:19 -0700, Francisco Jerez wrote: > Samuel Iglesias Gonsálvez writes: > > > > > From: Iago Toral Quiroga > > > > In fp64 we can produce code like this: > > > > mov(16) vgrf2<2>:UD, vgrf3<2>:UD > > > > That our simd lowering

Re: [Mesa-dev] [PATCH v2 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

Francisco Jerez writes: > Samuel Iglesias Gonsálvez writes: > >> From: Iago Toral Quiroga >> >> In fp64 we can produce code like this: >> >> mov(16) vgrf2<2>:UD, vgrf3<2>:UD >> >> That our simd lowering pass would typically split

Re: [Mesa-dev] [PATCH v2 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

Samuel Iglesias Gonsálvez writes: > From: Iago Toral Quiroga > > In fp64 we can produce code like this: > > mov(16) vgrf2<2>:UD, vgrf3<2>:UD > > That our simd lowering pass would typically split in instructions with a > width of 8, writing to two

[Mesa-dev] [PATCH v2 3/6] i965/fs/gen7: split instructions that run into exec masking bugs

From: Iago Toral Quiroga In fp64 we can produce code like this: mov(16) vgrf2<2>:UD, vgrf3<2>:UD That our simd lowering pass would typically split in instructions with a width of 8, writing to two consecutive registers each. Unfortunately, gen7 hardware has a bug affecting