[Mesa-dev] [PATCH v3 09/24] i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

2017-02-14 Thread Samuel Iglesias Gonsálvez
From: "Juan A. Suarez Romero" According to the IVB and HSW PRMs: "2.When the destination requires two registers and the sources are indirect, the sources must use 1x1 regioning mode." So for DF instructions the execution size is not limited by the number of address registers that are available

Re: [Mesa-dev] [PATCH v3 09/24] i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT

2017-02-15 Thread Francisco Jerez
Samuel Iglesias Gonsálvez writes: > From: "Juan A. Suarez Romero" > > According to the IVB and HSW PRMs: > > "2.When the destination requires two registers and the sources are > indirect, the sources must use 1x1 regioning mode." > > So for DF instructions the execution size is not limited by t