https://bugs.freedesktop.org/show_bug.cgi?id=105494
Tapani Pälli changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
From: Dave Airlie
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 0eeb2ca58ea..f6f0734dfda 100644
--- a/src/compiler/shader_info.
From: Dave Airlie
This fixes the fmask descriptor generation to handle 2d ms arrays.
---
src/amd/vulkan/radv_image.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 5ac0f72589d..669001085bc 100644
--- a/src/amd/v
This series does some refactoring and fixes to enable support
for storage image multisample.
It passes all the CTS tests except for some which look like
possible test bugs
(dEQP-VK.pipeline.multisample.storage_image.*r8g8b8a8_unorm*)
This doesn't fix the image to image copies for multisample,
but
From: Dave Airlie
This enables multisample shader storage images on radv.
---
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_formats.c | 3 +--
src/amd/vulkan/radv_shader.c | 2 ++
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd
From: Dave Airlie
If an image is going to be used as a storage image we want to
make sure the fmask is initialised to the correct value.
This initialises fmask on the undefined transition.
---
src/amd/vulkan/radv_cmd_buffer.c | 36
1 file changed, 36 inserti
From: Dave Airlie
We don't ever want to do the fmask lookup on a atomic or
store, the fmask should have been decompressed if the
surface has been moved to IMAGE_LAYOUT
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to
From: Dave Airlie
This just moves this out for later reuse.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index
Reviewed-by: Bas Nieuwenhuizen
On Mon, Mar 19, 2018 at 5:30 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> If a shader only writes to an output via a constant initializer we
> need to lower it before we call nir_remove_dead_variables so that
> this pass sees the stores from the initializer and
Reviewed-by: Bas Nieuwenhuizen
On Mon, Mar 19, 2018 at 4:42 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes:
> dEQP-VK.multiview.input_attachments*
> ---
> src/amd/vulkan/radv_shader_info.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/rad
Hi Lepton,
On Sat, Mar 17, 2018 at 3:09 AM, Lepton Wu wrote:
> If user calls map twice for kms_sw_displaytarget, the first mapped
> buffer could get leaked. Instead of calling mmap every time, just
> reuse previous mapping. Since user could map same displaytarget with
> different flags, we have t
Reviewed-by: Samuel Pitoiset
On 03/19/2018 04:42 AM, Dave Airlie wrote:
From: Dave Airlie
This fixes:
dEQP-VK.multiview.input_attachments*
---
src/amd/vulkan/radv_shader_info.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader_info.c
b/src/a
Reviewed-by: Samuel Pitoiset
On 03/19/2018 05:30 AM, Dave Airlie wrote:
From: Dave Airlie
If a shader only writes to an output via a constant initializer we
need to lower it before we call nir_remove_dead_variables so that
this pass sees the stores from the initializer and doesn't kill the
ou
Series is:
Reviewed-by: Samuel Pitoiset
On 03/19/2018 02:32 AM, Dave Airlie wrote:
From: Dave Airlie
For each view bit we need to emit a timestamp query.
Fixes: dEQP-VK.multiview.queries*
---
src/amd/vulkan/radv_query.c | 79 -
1 file changed,
Build mesa 7216 failed
Commit 929a4473d4 by Samuel Pitoiset on 3/14/2018 8:46 AM:
Revert "mesa: do not trigger _NEW_TEXTURE_STATE in glActiveTexture()"\n\nThis reverts commit f314a532fdc7af8381586144d2631d9968331f05.\n\nThis appears to introduce some blinking t
Hello list,
as the internal testing we do took too much time, and the nominated list grew a
bit, and there were a request to include a couple of nominated patches in the
release, plus a mistakenly rejected patch when it actually could be enqueued,
I've updated the RC with more patches (see inline
Exposing the visual makes following dEQP tests pass on Android:
dEQP-EGL.functional.wide_color.window__colorspace_srgb
dEQP-EGL.functional.wide_color.pbuffer__colorspace_srgb
Visual is exposed only when DRI_LOADER_CAP_RGBA_ORDERING is set.
Signed-off-by: Tapani Pälli
---
src/mesa
Add format definition and required plumbing to create images.
Note that there is no match to drm_fourcc definition, just like
with existing _DRI_IMAGE_FOURCC_SARGB.
Signed-off-by: Tapani Pälli
---
include/GL/internal/dri_interface.h| 2 ++
src/loader/loader_dri3_helper.c| 2 ++
s
i965 and gallium handle the atomic buffer index differently. It was
just by luck that the single piglit test for this was passing.
For gallium we use the atomic binding so that we match the handling
in st_bind_atomics().
On radeonsi this fixes the CTS test:
KHR-GL43.shader_storage_buffer_object.a
Mesa 18.0.0 has not been released yet, so let's extend 17.3 lifetime.
CC: Andres Gomez
CC: Emil Velikov
---
docs/release-calendar.html | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 25408c3604b..6a98d86432
This extension just removes restrictions on minDepth/maxDepth,
minDepthBounds/maxDepthBounds and VkClearDepthStencilValue::depth.
As we don't clamp anything, we can enable the extension for free.
The two following CTS tests now pass:
dEQP-VK.draw.inverted_depth_ranges.nodepthclamp_depth_range_unr
On Mon, 2018-03-19 at 13:56 +0100, Juan A. Suarez Romero wrote:
> Mesa 18.0.0 has not been released yet, so let's extend 17.3 lifetime.
>
> CC: Andres Gomez
> CC: Emil Velikov
> ---
> docs/release-calendar.html | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/doc
That doesn't fix the test for me. Are you sure it's a regression?
On 03/19/2018 06:08 AM, Dave Airlie wrote:
From: Dave Airlie
This pretty much reverts:
f3275ca01cddd5d1e999e3805eff42e06ce6e974
Author: Samuel Pitoiset
Date: Thu Mar 1 11:54:22 2018 +0100
ac/nir: only enable used chann
This one is similar to the negative viewport height feature
introduced by VK_KHR_maintenance1. Though, both extensions
can't be enabled at the same time.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 21 +
src/amd/vulkan/radv_extensions.py | 1 +
2 f
I think we still need to support image->image copies with depth
outside the range [0,1]. There was no explicit restriction on that,
but before enabling this it is impossible to get an image with depth
not in [0,1] so we did not have to care. But the gfx path uses the
depth HW with no depth bound so
Gen 7 GPUs store the compressed EAC/ETC2 images in other non-compressed
formats that can render. When GetCompressed* functions are called, the
pixels are returned in the non-compressed format that is used for the
rendering.
With this patch we store both the compressed and non-compressed versions
o
On Mon, 2018-03-19 at 16:00 +0200, Andres Gomez wrote:
> On Mon, 2018-03-19 at 13:56 +0100, Juan A. Suarez Romero wrote:
> > Mesa 18.0.0 has not been released yet, so let's extend 17.3 lifetime.
> >
> > CC: Andres Gomez
> > CC: Emil Velikov
> > ---
> > docs/release-calendar.html | 8 +++-
>
The reason they cannot be enabled at the same time is because the
behavior was different. I see nothing about using the AMD behavior in
this patch? Also since IIRC maintenance1 is core in vulkan 1.1 we
cannot reasonably expose the AMD ext if the instance was created with
vulkan >= 1.1
On Mon, Mar
Mesa 18.0 series has not been released yet, so let's extend 17.3 lifetime.
v2: add 17.3.9 in the calendar (Andres Gomez)
CC: Andres Gomez
CC: Emil Velikov
---
docs/release-calendar.html | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/docs/release-calendar.htm
This is:
Reviewed-by: Andres Gomez
On Mon, 2018-03-19 at 16:28 +0100, Juan A. Suarez Romero wrote:
> Mesa 18.0 series has not been released yet, so let's extend 17.3 lifetime.
>
> v2: add 17.3.9 in the calendar (Andres Gomez)
>
> CC: Andres Gomez
> CC: Emil Velikov
> ---
> docs/release-cale
In the short imm form 0x8 was sign-extended to 0xfff8 which leads to
wrong results.
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_e
In the short imm form 0x8 was sign-extended to 0xfff8 which leads to
wrong results.
Fix setting the NOT modifier on immediate sources as well, because this is not
legal anyway.
v2: add an assert and move setting the NOT modifier
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouve
The previous commit to make DRI3 modifier support optional, breaks with
an updated server and old client.
Make sure we never set multibuffers_available unless we also support it
locally. Make sure we don't call stubs of new-DRI3 functions (or empty
branches) which will never succeed.
Signed-off-b
I mainly cleaned the series and implemented missing features or fixed stuff:
* converted to C style comments
* added nv50 support
* added interpolateAt
* fixed Arrays of Images
* fixed Images on pre Maxwell GPUs
* disable MS Images when using NIR
Piglit pass rates are pretty good. With Fermi/Keple
this is required for Drivers which don't allow reading from outputs.
Reviewed-by: Timothy Arceri
Signed-off-by: Karol Herbst
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracke
this is mostly usefull for lazy IR converters not wanting to deal with 64 bit
lowering and other illegal stuff
v5: also handle SAT
v6: rename type variables
fixed lowering of NEG
add lowering of NOT
Reviewed-by: Pierre Moreau
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/
this makes debugging the shader header a little easier
Acked-by: Pierre Moreau
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/
v2: remove TGSI related bits
Signed-off-by: Karol Herbst
Reviewed-by: Pierre Moreau
---
src/gallium/drivers/nouveau/Makefile.sources | 2 +
.../nouveau/codegen/nv50_ir_from_common.cpp| 107 +
.../drivers/nouveau/codegen/nv50_ir_from_common.h | 58 ++
not all those nir options are actually required, it just made the work a
little easier.
v2: fix asserts
parse compute shaders
don't lower bitfield_insert
v3: fix memory leak
v4: don't lower fmod32
v5: set lower_all_io_to_temps to false
fix memory leak because we take over ownership of
From: Connor Abbott
In order to reduce moves when coalescing multiple registers into a
larger register, RA will try to coalesce MERGE instructions with their
definitions. For example, for something like this in GLSL:
uint a = ...;
uint b = ...;
uint64 x = packUint2x32(a, b);
The compiler will t
v2: add helper function for indirects
v4: add new getIndirect overload for easier use
v5: use getSSA for ssa values
we can just create the values for unassigned registers in getSrc
v6: always create at least 32 bit values
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_fr
v4: treat imul as unsigned
v5: remove pointless !!
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 115 +
1 file changed, 115 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouve
v2: add support for geometry shaders
set idx
add some missing mappings
fix for 64bit inputs/outputs
fix up some FP color output index messup
parse centroid flag
v3: fix arrays in outputs as well
fix input/ouput size calculation for tessellation shaders
v4: add getSlotAddress
v2: parse a few more fields
v3: add special handling for GL_ISOLINES
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 60 ++
1 file changed, 60 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gall
v2: add constant_folding
v6: print non final NIR only for verbose debugging
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 39 ++
1 file changed, 39 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/s
Signed-off-by: Karol Herbst
v2: user bitfield_insert instead of bfi
rework switch helper macros
remove some lowering code (LoweringHelper is now used for this)
v3: add pack_half_2x16_split
add unpack_half_2x16_split_x/y
v5: replace first argument with nullptr in loadImm calls
pref
v2: allow for non debug builds as well
v3: move reading out env var more global
disable tg4 with multiple offsets with nir
disable caps for 64 bit types
v6: nv50 support
disable MS images
disable bindless textures
Acked-by: Pierre Moreau
Signed-off-by: Karol Herbst
---
src/galli
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 24 ++
1 file changed, 24 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 008beb9a02a..eb
a lot of those fields are not valid for a lot of tex ops. Not quite sure if
it's worth the effort to check for those or just keep it like that. It seems
to kind of work.
v2: reworked offset handling
add tex support with indirect R/S arguments
handle GLSL_SAMPLER_DIM_EXTERNAL
drop refer
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 04a0f03ae2f..2bd4
v3: add workaround for RA issues
indirects have to be multiplied by 0x10
fix indirect access
v4: use smarter getIndirect helper
use storeTo helper
v5: don't use const_offset directly
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 46 +
v2: use new getIndirect helper
fixes symbols for 64 bit types
v4: use smarter getIndirect helper
simplify address calculation
use loadFrom helper
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++
1 file changed, 10 insertions(+)
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp| 17 +
1 file changed, 17 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 2a9c0929e90..3b
v3: and load_output
v4: use smarter getIndirect helper
use new getSlotAddress helper
v5: don't use const_offset directly
fix for indirects
v6: add support for interpolateAt
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 97 ++
1 f
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index a10038f9a88..2a
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 72 ++
1 file changed, 72 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 8d547dbbea4..d4
v6: fix loops with blocks at the end nothing points to
skip blocks with no instructions and no predecessors
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 270 -
1 file changed, 268 insertions(+), 2 deletions(-)
diff --git a/src/gall
v2: support more sys values
fixed a bug where for multi component reads all values ended up in x
v3: add load_patch_vertices_in
v4: add subgroup stuff
v5: add helper invocation
v6: fix loading 64 bit system values
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.c
we store those arrays in local memory and reserve some space for each of the
arrays. The arrays are stored in a packed format, because we know quite easily
the context of each index. We don't do that in TGSI so far.
This causes various issues to come up in the MemoryOpt pass, because ld/st with
in
v4: use loadFrom helper
v5: support indirect buffer access
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 90 ++
1 file changed, 90 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/driver
v5: add more barrier intrinsics
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_f
v2: use mkOp
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 43a1
v4: use smarter getIndirect helper
use new getSlotAddress helper
v5: use loadFrom helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 23 ++
1 file changed, 23 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 19086157baa..2f831bfe487
v2: add vote_eq support
use the new subop intrinsic helper
add ballot
v3: add read_(first_)invocation
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 42 ++
1 file changed, 42 insertions(+)
diff --git a/src/gallium/drivers/nouveau
v4: use smarter getIndirect helper
use new getSlotAddress helper
use loadFrom helper
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 27 ++
1 file changed, 27 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_
v4: use loadFrom helper
Signed-off-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cp
v3: fix compiler warnings
v4: use loadFrom helper
v5: fix signed min/max
v6: set tex mask
add support for indirect image access
set cache mode
Signed-off-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 395 +++--
1 file changed, 375 insertions(+)
Build mesa 7217 completed
Commit e10dc12f6f by Jose Fonseca on 3/19/2018 3:41 PM:
scons: need to split CC or things might fail\n\nWe've seen this fail internally.\n\nReviewed-by: Roland Scheidegger
Configure your notification preferences
___
Hi,
>> This is a RFC because I don't really know what I'm doing here. But we
>> have this problem with AMD and KWin already for quite a long time and
>> I hope it can be fixed now.
> If index_size > 0, indexbuf should always be non-NULL. This is a bug
> somewhere else.
I've also been bitten by th
On the CI family, firmware requires the destory command have to be the
last command in the IB, moving feedback command after destroy is causing
issues on CI cards, so we have to keep the previous logic that moves
destroy back to the last command.
But as the original issue fixed previously, with th
Quoting Jason Ekstrand (2018-03-17 23:37:51)
> On Sat, Mar 17, 2018 at 10:32 PM, Dylan Baker wrote:
>
> Quoting Jason Ekstrand (2018-03-17 09:53:13)
> > On March 16, 2018 23:36:50 Dylan Baker wrote:
> >
> > > Quoting Rob Clark (2018-03-16 14:25:09)
> > >> On Fri, Mar 16, 2018
If user calls map twice for kms_sw_displaytarget, the first mapped
buffer could get leaked. Instead of calling mmap every time, just
reuse previous mapping. Since user could map same displaytarget with
different flags, we have to keep two different pointers, one for rw
mapping and one for ro mappin
Add a new struct kms_sw_plane which delegate a plane and use it
in place of sw_displaytarget. Multiple planes share same underlying
kms_sw_displaytarget.
Reviewed-by: Tomasz Figa
Reviewed-by: Emil Velikov
Signed-off-by: Lepton Wu
---
.../winsys/sw/kms-dri/kms_dri_sw_winsys.c | 152
This series fix several issues that happen when running "./autogen.sh && make
{dist, distcheck}".
The first two patches in the series is a new fix for issue
https://bugs.freedesktop.org/show_bug.cgi?id=105211, as the current version
breaks when running the above command, due "make dist/distcheck"
This reverts commit 61d6ff3ba3c0a21239641f4d5fe8d4fa9c864325.
We need to unconditionally check for wayland-scanner, so make
dist/distcheck is not broken.
CC: Daniel Stone
---
configure.ac | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/configure.ac b/configure
Build vulkan/wsi/wayland if Wayland platform is enabled.
CC: Daniel Stone
Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211
---
configure.ac | 7 +--
src/vulkan/Makefile.am | 4
2 files changed,
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 55143dbc66a..5150f56b6a9 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@
---
src/amd/vulkan/Makefile.sources | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index b0a8f8b97d8..ccb956a2396 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -83,5 +83
---
src/amd/vulkan/Makefile.am | 4
src/intel/Makefile.vulkan.am | 4
2 files changed, 8 insertions(+)
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index cc1b53980fd..00b808229fa 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -23,6
---
src/gallium/drivers/swr/Makefile.am | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/swr/Makefile.am
b/src/gallium/drivers/swr/Makefile.am
index 13c7f8b7345..5ec9213c349 100644
--- a/src/gallium/drivers/swr/Makefile.am
+++ b/src/gallium/drivers/swr/Makefile.am
@@ -368,6
---
Makefile.am | 1 +
src/gallium/winsys/tegra/drm/Makefile.sources | 1 +
2 files changed, 2 insertions(+)
diff --git a/Makefile.am b/Makefile.am
index de6921bf1fc..804b1d85353 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -75,6 +75,7 @@ noinst_HEADERS = \
Load NIR compiler headers from srcdir, not builddir.
---
src/gallium/drivers/vc4/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc4/Makefile.am
b/src/gallium/drivers/vc4/Makefile.am
index d65bf20e26d..abcad54f087 100644
--- a/src/gallium/driver
Hi Lepton,
On 19 March 2018 at 17:33, Lepton Wu wrote:
> If user calls map twice for kms_sw_displaytarget, the first mapped
> buffer could get leaked. Instead of calling mmap every time, just
> reuse previous mapping. Since user could map same displaytarget with
> different flags, we have to keep
https://bugs.freedesktop.org/show_bug.cgi?id=105444
Jordan Justen changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Set this environment variable to disable multithreading:
GALLIUM_THREAD=0
Marek
On Mon, Mar 19, 2018 at 1:05 PM, Clemens Eisserer
wrote:
> Hi,
>
> >> This is a RFC because I don't really know what I'm doing here. But we
> >> have this problem with AMD and KWin already for quite a long time and
This reverts commit c0ed52f6146c7e24e1275451773bd47c1eda3145. It was
preventing the image format validation from being done on buffer
textures, which is required to ensure that the application doesn't
attempt to create a buffer texture with an internal format
incompatible with the image unit forma
The buffer texture size calculations (should be easy enough, right?)
are repeated in three different places, each of them subtly broken in
a different way. E.g. the image load/store path was never fixed to
clamp to MaxTextureBufferSize, and none of them are taking into
account the buffer offset co
Otherwise the specified surface state will allow the GPU to access
memory up to BufferOffset bytes past the end of the buffer. Found by
inspection.
Cc: mesa-sta...@lists.freedesktop.org
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Instead of directly using intel_obj->buffer. Among other things
intel_bufferobj_buffer() will update intel_buffer_object::
gpu_active_start/end, which are used by glBufferSubData() to decide
which path to take. Fixes a failure in the Piglit
ARB_shader_image_load_store-host-mem-barrier Buffer Upda
---
src/compiler/nir/nir_builder_opcodes_h.py | 4 +-
src/compiler/nir/nir_intrinsics.py| 865 +++---
src/compiler/nir/nir_intrinsics_c.py | 4 +-
src/compiler/nir/nir_intrinsics_h.py | 4 +-
4 files changed, 450 insertions(+), 427 deletions(-)
diff
On 19 March 2018 at 17:49, Juan A. Suarez Romero wrote:
> Load NIR compiler headers from srcdir, not builddir.
> ---
> src/gallium/drivers/vc4/Makefile.am | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/vc4/Makefile.am
> b/src/gallium/drivers/vc4/Make
On 19 March 2018 at 17:49, Juan A. Suarez Romero wrote:
> This series fix several issues that happen when running "./autogen.sh && make
> {dist, distcheck}".
>
Sigh, I should really send local patches as soon as I write them - 1-6
have been sitting locally for about a week :-\
1-7 are
Reviewed-by
On 20 March 2018 at 01:36, Daniel Stone wrote:
> The previous commit to make DRI3 modifier support optional, breaks with
> an updated server and old client.
>
> Make sure we never set multibuffers_available unless we also support it
> locally. Make sure we don't call stubs of new-DRI3 functions (o
https://bugs.freedesktop.org/show_bug.cgi?id=105494
almos changed:
What|Removed |Added
Status|RESOLVED|REOPENED
Resolution|FIXED
On Mon, Mar 19, 2018 at 10:55 AM, Emil Velikov wrote:
> Hi Lepton,
>
> On 19 March 2018 at 17:33, Lepton Wu wrote:
>> If user calls map twice for kms_sw_displaytarget, the first mapped
>> buffer could get leaked. Instead of calling mmap every time, just
>> reuse previous mapping. Since user could
Generalize the code for remove dead loops to also remove dead if
nodes. The conditions are the same in both cases, if the node (and
it's children) don't have side-effects AND the nodes after it don't
use the values produced by the node.
The only difference is when evaluating side effects: loops co
From: Dave Airlie
We have some cases where in subpass we want the layer but having
it be 0 and loaded in the frag shader without the vertex shader
exporting it is fine.
So don't export the layer if we don't have a value to put in it.
Fixes: d4c74aed7a8 (radv/multiview: mark layer_input if we ha
From: Dave Airlie
It appears its quite legal to do image copies on multisample
images, however due to a bug in our txf handling and incomplete
tests we never actually noticed we didn't do it properly in radv.
This patch implements a compute shader to copy multiple samples
of an image to another
From: Dave Airlie
This opcode is used to retrieve the fmask value for the pixel,
we need this to write some meta shaders for multisample image
copies.
---
src/amd/common/ac_nir_to_llvm.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac
1 - 100 of 150 matches
Mail list logo
