[Mesa-dev] [PATCH 22/22] nir/spirv: handle OpBitcasts for pointers

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 5 +- src/compiler/spirv/vtn_alu.c | 187 +- src/compiler/spirv/vtn_private.h | 3 + 3 files changed, 115 insertions(+), 80 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b

[Mesa-dev] [PATCH 02/22] nir: replace nir_load_system_value calls with appropiate builder functions

this helps reduce the overall code changes when a bit_size parameter is added to nir_load_system_value Reviewed-by: Jason Ekstrand Reviewed-by: Eric Anholt Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_buffer.c| 8 src/amd/vulkan/radv_meta_bufimage.c

[Mesa-dev] [PATCH 01/22] nir: add const_index parameters to system value builder function

this allows to replace some nir_load_system_value calls with the specific system value constructor Reviewed-by: Jason Ekstrand Reviewed-by: Eric Anholt Signed-off-by: Karol Herbst --- src/compiler/nir/nir_builder_opcodes_h.py | 21 +++-- 1 file changed, 19 insertions(+), 2

[Mesa-dev] [PATCH 14/22] nir: add legal bit_sizes to intrinsics

values. Also this allows for further validation Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h | 3 +++ src/compiler/nir/nir_intrinsics.py | 15 ++- src/compiler/nir/nir_intrinsics_c.py | 6 +- src/nouveau/meson.build | 25

[Mesa-dev] [PATCH 20/22] nir/spirv: physical pointer support

hacky, but it is much smaller than what we had with the fat ptr approach and I don't have to add a new phys_pointer value type, which made things a lot easier. Signed-off-by: Karol Herbst --- src/compiler/nir/nir.c| 4 +- src/compiler/nir/nir.h| 9

[Mesa-dev] [PATCH 19/22] nir/spirv: handle kernel function parameters

inputs match uniforms in most ways and we can just take advantage of most of nir_lower_io Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 32 +++ 1 file changed, 32 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler

[Mesa-dev] [PATCH 09/22] glsl: add cl_size and cl_alignment

Signed-off-by: Karol Herbst --- src/compiler/glsl_types.cpp | 48 + src/compiler/glsl_types.h | 10 src/compiler/nir_types.cpp | 12 ++ src/compiler/nir_types.h| 4 4 files changed, 74 insertions(+) diff --git a/src/compiler

[Mesa-dev] [PATCH 07/22] glsl: add packed for struct types

We need this for OpenCL kernels because we have to apply C rules for alignment and padding inside structs and for this we also have to know if a struct is packed or not. Signed-off-by: Karol Herbst --- src/compiler/glsl_types.cpp | 17 +++-- src/compiler/glsl_types.h

[Mesa-dev] [PATCH 13/22] nir/spirv: parse memory model

Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h| 8 src/compiler/nir/nir_clone.c | 1 + src/compiler/nir/nir_serialize.c | 2 ++ src/compiler/spirv/spirv_to_nir.c | 15 +-- 4 files changed, 24 insertions(+), 2 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 03/22] nir/spirv: initial handling of OpenCL.std extension opcodes

Not complete, mostly just adding things as I encounter them in CTS. But not getting far enough yet to hit most of the OpenCL.std instructions. Anyway, this is better than nothing and covers the most common builtins. Signed-off-by: Karol Herbst --- src/compiler/nir/meson.build | 1

[Mesa-dev] [PATCH 12/22] nir: add type alignment support to lower_io

From: Rob Clark For cl we can have structs with 8/16/32/64 bit scalar types (as well as, ofc, arrays/structs/etc), which are padded according to 'C' rules. So for lowering struct deref's we need to not just consider a field's size, but also it's alignment. Signed-off-by: Karol Herbst --- src

[Mesa-dev] [PATCH 17/22] nir: rename global to private memory

ed across all thrads of a work group the solution where everybody could be happy with is to rename "global" to "private" and use "global" later for memory usually stored within system accessible memory (be it VRAM or system RAM if keeping SVM in mind). Signed-

[Mesa-dev] [PATCH 04/22] nir/spirv: add OpIsFinite and OpIsNormal

From: Rob Clark changes by Karol: v2: make compatible with 64 bit floats fix isfinite v3: use snake_case. Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_alu.c | 32 1 file changed, 32 insertions(+) diff --git a/src/compiler/spirv/vtn_alu.c b/src

[Mesa-dev] [PATCH 10/22] nir/vtn: add caps for some cl related capabilities

From: Rob Clark vtn supports these, so don't squalk if user is happy with enabling these. Signed-off-by: Karol Herbst --- src/compiler/shader_info.h | 3 +++ src/compiler/spirv/spirv_to_nir.c | 16 +--- src/compiler/spirv/vtn_variables.c | 6 -- 3 files changed, 20

[Mesa-dev] [PATCH 15/22] nir: add support for address bit sized system values

Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_buffer.c | 8 ++-- src/amd/vulkan/radv_meta_bufimage.c | 16 src/amd/vulkan/radv_meta_fast_clear.c | 4 +- src/amd/vulkan/radv_meta_resolve_cs.c | 4 +- src/amd/vulkan/radv_query.c

[Mesa-dev] [PATCH 16/22] nir+vtn: vec8+vec16 support

instructions that take more than 4 srcs (ie vec8 and vec16), nir_build_alu() is has nir_build_alu_tail() split out and re-used by nir_build_alu2() (which is used for the > 4 src args case). Signed-off-by: Rob Clark Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h |

[Mesa-dev] [PATCH 08/22] glsl: add glsl_base_get_byte_size

Signed-off-by: Karol Herbst --- src/compiler/glsl_types.h | 34 ++ src/compiler/nir_types.h | 30 +- 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h index

[Mesa-dev] [PATCH 06/22] vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 3 +++ src/compiler/spirv/vtn_private.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 2c214324774..650eb6a977c 100644 --- a/src/compiler

[Mesa-dev] [PATCH 11/22] nir: simplify get_io_offset() parameters

From: Rob Clark For pointers we'll need to add another caller, plus in addition a type_align() fxn ptr. So just simplify things and pass the lower_io_state to get_io_offset(). Signed-off-by: Karol Herbst --- src/compiler/nir/nir_lower_io.c | 12 ++-- 1 file changed, 6 insertions

[Mesa-dev] [PATCH 18/22] nir/spirv: handle SpvStorageClassCrossWorkgroup

Signed-off-by: Karol Herbst --- src/compiler/nir/nir.c | 4 src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_print.c | 2 ++ src/compiler/spirv/vtn_private.h | 1 + src/compiler/spirv/vtn_variables.c | 4 5 files changed, 12 insertions(+) diff --git

[Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

v2: fix for specialization constants as well Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 20 src/compiler/spirv/vtn_alu.c | 11 +++ 2 files changed, 31 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv

[Mesa-dev] [PATCH 21/22] spirv/cl: support vload/vstore

Signed-off-by: Karol Herbst --- src/compiler/spirv/vtn_opencl.c | 59 + 1 file changed, 59 insertions(+) diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c index 089e6168fd8..ecaca4c17bc 100644 --- a/src/compiler/spirv/vtn_opencl.c

[Mesa-dev] [PATCH 00/22] nir/spirv: support for CL kernel

or how the derefs for pointers are created. But overall it feels we require less changes overall with my new approach to support physical pointers inside nir and vtn. Karol Herbst (18): nir: add const_index parameters to system value builder function nir: replace nir_load_system_value calls

Re: [Mesa-dev] [PATCH 05/22] nir/spirv: cast shift operand to u32

Jason Ekstrand wrote: >> >> Reviewed-by: Jason Ekstrand >> Cc: mesa-sta...@lists.freedesktop.org >> >> On Tue, Nov 13, 2018 at 9:48 AM Karol Herbst wrote: >>> >>> v2: fix for specialization constants as well >>> >>>

[Mesa-dev] [PATCH] gm107/ir: fix compile time warning in getTEXSMask

In function 'uint8_t nv50_ir::getTEXSMask(uint8_t)': warning: control reaches end of non-void function [-Wreturn-type] Reported-by: Moiman@freenode Fixes: f821e80213e38e93f96255b3deacb737a600ed40 "gm107/ir: use scalar tex instructions where possible" Signed-off-by: Karol Herbst

Re: [Mesa-dev] [PATCH v2 2/2] i965: Implement ARB_compute_variable_group_size.

need from > nir_lower_system_values.c to master. > > Thank you, > Pam > > On Thu, Jun 28, 2018 at 5:50 AM, Karol Herbst wrote: >> >> Hi, >> >> if the changes inside "src/compiler/nir/nir_lower_system_values.c" are >> extracted into a seperate patch, this patch

Re: [Mesa-dev] [PATCH] gm107/ir: fix compile time warning in getTEXSMask

On Wed, Nov 7, 2018 at 3:21 PM Ilia Mirkin wrote: > > Reviewed-by: Ilia Mirkin > > Although I'd rather the return go into the "default:" case, after the > assert, which is the reason for the warning. sure, I'll move it. > On Wed, Nov 7, 2018 at 7:50 AM Karol Herbst

Re: [Mesa-dev] [PATCH 3/8] nir/builder: Add iadd_imm and imul_imm helpers

Reviewed-by: Karol Herbst On Wed, Nov 14, 2018 at 12:23 AM Jason Ekstrand wrote: > > The pattern of adding or multiplying an integer by an immediate is > fairly common especially in deref chain handling. This adds a helper > for it and uses it a few places. The advantage t

Re: [Mesa-dev] [PATCH 7/8] nir: Add alignment parameters to SSBO, UBO, and shared access

I like the general idea, we just shouldn't rely too much on the type size later on, especially in regards to CL where we can have unaligned load/stores especially for packed structs. Acked-by: Karol Herbst On Wed, Nov 14, 2018 at 12:24 AM Jason Ekstrand wrote: > > This also changes spirv_

Re: [Mesa-dev] [PATCH] nv50,nvc0: guard against zero-size blits

Reviewed-by: Karol Herbst On Sun, Oct 7, 2018 at 11:50 PM Ilia Mirkin wrote: > > The current state tracker can generate these sometimes. Fixing this is > more involved, and due to some integer math we can generate > divisions-by-zero. > > Signed-off-by: Ilia Mirk

Re: [Mesa-dev] [PATCH] nvc0: fix blitting red to srgb8_alpha

just asking, because your commit message more or less hinted towards that being about r -> srgb conversions, but it makes sense that any single component blits wouldn't work. Reviewed-by: Karol Herbst On Tue, Oct 9, 2018 at 1:03 PM Ilia Mirkin wrote: > > Ones that blit to srgb, yes.

Re: [Mesa-dev] [PATCH] nvc0: fix blitting red to srgb8_alpha

but this movs all single color blits to the 3d blitter, right? On Sun, Oct 7, 2018 at 11:50 PM Ilia Mirkin wrote: > > For some reason the 2d engine can't handle this. Red formats get special > treatment there, so perhaps related. > > Fixes dEQP-GLES3 tests of the form: > >

Re: [Mesa-dev] [PATCH] nvc0: fix blitting red to srgb8_alpha

yeah, no. Everything should be handled. Got a little bit confused with the luminance check. On Tue, Oct 9, 2018 at 4:07 PM Ilia Mirkin wrote: > > What other single component formats are there that aren't covered by the > earlier ifs? > > On Tue, Oct 9, 2018, 07:49 Karo

Re: [Mesa-dev] [PATCH mesa 2/6] nouveau: silence paranoid compiler's -Wclass-memaccess

yeah, I agree here. Either the code was wrong in the first place, which means it would have to be fixed properly or the warning is wrong. The proper fix here is that GCC should detect itself if it's safe to do or not, otherwise that warning becomes a "might be a problem" thing which doesn't help

Re: [Mesa-dev] [PATCH mesa 2/6] nouveau: silence paranoid compiler's -Wclass-memaccess

tor and non-trivial copy-constructor. > The original code is broken in the way it mixes C and C++ initialization and > the patch only papers over the issue. > The correct fix would be to provide a proper constructor for structs that > include instances of C++ classes. > > Jan >

[Mesa-dev] [PATCH] glsl/lower_output_reads: set invariant and precise flags on temporaries

.functional.shaders.invariance.lowp.common_subexpression_2 dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3 Signed-off-by: Karol Herbst --- src/compiler/glsl/lower_output_reads.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/lower_output_reads.cpp b/src/compiler/glsl

Re: [Mesa-dev] [PATCH] nv50,nvc0: mark textures dirty on fb update

Reviewed-by: Karol Herbst On Mon, Jan 21, 2019 at 4:27 AM Ilia Mirkin wrote: > > We may have to flush the cache if there are any textures presently bound > that refer to the outgoing framebuffer. This is only checked at > validation time. > > Fixes a nu

[Mesa-dev] [PATCH] glsl/lower_output_reads: set invariant and precise flags on temporaries

.functional.shaders.invariance.lowp.common_subexpression_2 dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3 Signed-off-by: Karol Herbst --- src/compiler/glsl/lower_output_reads.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/lower_output_reads.cpp b/src/compiler/glsl

[Mesa-dev] [PATCH 2/2] nvc0/ir: replace cvt instructions with add to improve shader performance

inst cvts bytes helped 0 0 0 0 14037 0 hurt 0 0 0 0 0 0 Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 55 +++ .

[Mesa-dev] [PATCH 1/2] nvc0: count cvt instructions and print it

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_driver.h| 1 + .../drivers/nouveau/codegen/nv50_ir_inlines.h | 17 + .../drivers/nouveau/codegen/nv50_ir_target.cpp | 2 ++ src/gallium/drivers

Re: [Mesa-dev] [PATCH 2/2] nvc0/ir: replace cvt instructions with add to improve shader performance

On Fri, Dec 14, 2018 at 12:27 AM Ilia Mirkin wrote: > > On Thu, Dec 13, 2018 at 6:14 PM Karol Herbst wrote: > > > > gives me an performance boost of 0.2% in pixmark_piano on my gk106, gm204 > > and > > gp107. > > > > changes in shader-db: >

Re: [Mesa-dev] [PATCH 2/3] nv50/ir: optimize slct(b, c, set(a, 0)) to slct(b, c, a)

for On Sat, Dec 15, 2018 at 7:58 PM Ilia Mirkin wrote: > > On Fri, Dec 14, 2018 at 6:12 PM Karol Herbst wrote: > > > > From: Karol Herbst > > > > helps mainly feral ported games > > > > shader-db changes: > > total instructions in shared prog

Re: [Mesa-dev] [PATCH] nir: Document the function inlining process

sorry, totally forgot about that. Seems fine as it is and I have the same within my CL branch (except the last nir_lower_constant_initializers). as I don't really know if all that is actually true, but because it makes sense to me: Acked-by: Karol Herbst I kind of wished we would have a helper

[Mesa-dev] [PATCH v2] nvc0/ir: replace cvt instructions with add to improve shader performance

inst cvts bytes helped 0 0 0 0 14037 0 hurt 0 0 0 0 0 0 v2: only for 32 bit operations move some common code out of the switch handle OP_SAT with modifiers Signed-of

[Mesa-dev] [PATCH 3/3] nv50/ir: convert slct with boolean result to set

From: Karol Herbst helps mainly feral ported games changes in shader-db: total instructions in shared programs : 7565661 -> 7545812 (-0.26%) total gprs used in shared programs: 797213 -> 797088 (-0.02%) total shared used in shared programs : 639636 -> 639636 (0.00%) to

[Mesa-dev] [PATCH 2/3] nv50/ir: optimize slct(b, c, set(a, 0)) to slct(b, c, a)

From: Karol Herbst helps mainly feral ported games shader-db changes: total instructions in shared programs : 7614782 -> 7565661 (-0.65%) total gprs used in shared programs: 798045 -> 797213 (-0.10%) total shared used in shared programs : 639636 -> 639636 (0.00%) to

[Mesa-dev] [PATCH 1/3] nv50/ir: clean up src2 in ConstantFolding

no changes in shader-db Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index

Re: [Mesa-dev] [PATCH 7/8] gm107/ir: add lowering of atomic f32 add on shared memory

On Wed, Dec 5, 2018 at 6:30 AM Ilia Mirkin wrote: > > Signed-off-by: Ilia Mirkin > --- > .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 49 +++ > .../nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 + > 2 files changed, 50 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 7/8] gm107/ir: add lowering of atomic f32 add on shared memory

nvm, I somehow didn't notice that "if (atom->dType != TYPE_F32)" check... On Wed, Dec 5, 2018 at 3:43 PM Karol Herbst wrote: > > but uhm, how would that work if you assert(atom->subOp == > NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought > that's only

Re: [Mesa-dev] [PATCH 7/8] gm107/ir: add lowering of atomic f32 add on shared memory

but uhm, how would that work if you assert(atom->subOp == NV50_IR_SUBOP_ATOM_ADD); inside handleSharedATOMGM107? I thought that's only needed for fadd, not for all atoms On Wed, Dec 5, 2018 at 3:17 PM Ilia Mirkin wrote: > > On Wed, Dec 5, 2018 at 4:59 AM Karol Herbst wrote: > >

[Mesa-dev] [PATCH 03/12] nir/vtn: add caps for some cl related capabilities

From: Rob Clark vtn supports these, so don't squalk if user is happy with enabling these. Signed-off-by: Karol Herbst --- src/compiler/shader_info.h | 3 +++ src/compiler/spirv/spirv_to_nir.c | 17 ++--- src/compiler/spirv/vtn_variables.c | 6 -- 3 files changed, 21

[Mesa-dev] [PATCH 06/12] nir/spirv: handle SpvStorageClassCrossWorkgroup

Signed-off-by: Karol Herbst --- src/compiler/nir/nir.c | 4 src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_print.c | 2 ++ src/compiler/spirv/vtn_private.h | 1 + src/compiler/spirv/vtn_variables.c | 4 5 files changed, 12 insertions(+) diff --git

[Mesa-dev] [PATCH 05/12] nir: rename global/local to private/function memory

quot; memory is memory only accessible within a function, while SPIR-V "local" memory is memory accessible within the same workgroup. v2: rename local to function as well Signed-off-by: Karol Herbst --- src/amd/common/ac_nir_to_llvm.c | 6 ++-- src/amd/vulkan/radv_shader.c

[Mesa-dev] [PATCH 12/12] nir/spirv: handle ContractionOff execution mode

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_info.h| 1 + src/compiler/spirv/spirv_info_c.py | 1 + src/compiler/spirv/spirv_to_nir.c | 9 - src/compiler/spirv/vtn_alu.c | 4 ++-- src/compiler/spirv/vtn_cfg.c | 2 ++ src/compiler/spirv/vtn_private.h | 3

[Mesa-dev] [PATCH 01/12] mesa: add MESA_SHADER_KERNEL

used for CL kernels Signed-off-by: Karol Herbst --- src/amd/common/ac_nir_to_llvm.c| 4 ++-- src/compiler/nir/nir.c | 2 +- src/compiler/nir/nir_print.c | 7 ++- src/compiler/shader_enums.c| 5 - src

[Mesa-dev] [PATCH 08/12] nir/validate: allow to check against a bitmask of bit_sizes

Signed-off-by: Karol Herbst --- src/compiler/nir/nir_validate.c | 34 - 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c index 7ee13da258d..ef24e96ee3f 100644 --- a/src/compiler/nir

[Mesa-dev] [PATCH 04/12] nir/spirv: improve parsing of the memory model

Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h| 8 src/compiler/nir/nir_clone.c | 1 + src/compiler/nir/nir_serialize.c | 2 ++ src/compiler/spirv/spirv_to_nir.c | 26 ++ src/compiler/spirv/vtn_private.h | 3 +++ 5 files changed, 36

[Mesa-dev] [PATCH 02/12] vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst --- src/compiler/spirv/spirv_to_nir.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index f6a7cd6c4fd..2c2dbe12a3c 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv

[Mesa-dev] [PATCH 10/12] nir: add bit_size parameter to system values with multiple allowed bit sizes

Signed-off-by: Karol Herbst --- src/compiler/nir/nir_builder_opcodes_h.py | 14 -- src/compiler/nir/nir_lower_system_values.c| 4 ++-- src/gallium/drivers/vc4/vc4_nir_lower_blend.c | 4 ++-- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir

[Mesa-dev] [PATCH 11/12] nir: add support for address bit sized system values

Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_buffer.c | 8 ++-- src/amd/vulkan/radv_meta_bufimage.c| 28 +++--- src/amd/vulkan/radv_meta_clear.c | 4 +- src/amd/vulkan/radv_meta_fast_clear.c | 4 +- src/amd/vulkan/radv_meta_resolve_cs.c

[Mesa-dev] [PATCH 07/12] nir: replace more nir_load_system_value calls with builder functions

Signed-off-by: Karol Herbst --- src/amd/vulkan/radv_meta_bufimage.c | 12 ++-- src/amd/vulkan/radv_meta_clear.c| 4 ++-- src/amd/vulkan/radv_query.c | 4 ++-- src/gallium/auxiliary/nir/tgsi_to_nir.c | 3 +-- src/intel/compiler/brw_nir.c| 3 +-- 5

[Mesa-dev] [PATCH 00/12] Some cleaned up Compute patches

values * handle ContractionOff for compute kernels Karol Herbst (11): mesa: add MESA_SHADER_KERNEL vtn: handle SpvExecutionModelKernel nir/spirv: improve parsing of the memory model nir: rename global/local to private/function memory nir/spirv: handle SpvStorageClassCrossWorkgroup nir

[Mesa-dev] [PATCH 09/12] nir: add legal bit_sizes to intrinsics

of multiple possible values. v2: validate dest bit_size Signed-off-by: Karol Herbst --- src/compiler/nir/nir.h | 3 +++ src/compiler/nir/nir_intrinsics.py | 25 +++-- src/compiler/nir/nir_intrinsics_c.py | 6 +- src/compiler/nir/nir_validate.c | 6

[Mesa-dev] [PATCH 7/7] WIP: per context fences/pushbuf

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_buffer.c | 20 +++--- src/gallium/drivers/nouveau/nouveau_context.c | 33 - src/gallium/drivers/nouveau/nouveau_context.h | 17 ++--- src/gallium/drivers/nouveau/nouveau_fence.h | 5 +- src/gallium/drivers/nouveau

[Mesa-dev] [PATCH 3/7] nv50,nvc0: simplify screen.fence

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv50/nv50_screen.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_screen.h | 1 - src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 ++-- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 - 4 files changed, 4 insertions(+), 6

[Mesa-dev] [PATCH 5/7] WIP: buffered shader printing

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 1 + .../drivers/nouveau/codegen/nv50_ir_print.cpp | 67 --- .../drivers/nouveau/codegen/nv50_ir_util.h| 1 + 3 files changed, 46 insertions(+), 23 deletions(-) diff --git a/src/gallium/drivers

[Mesa-dev] [PATCH 4/7] nouveau: access client and pushbuf from context directly

prepareation for fixing our multi context issues. Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 ++-- src/gallium/drivers/nouveau/nv30/nv30_draw.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_compute.c | 4 ++-- src/gallium/drivers/nouveau/nv50

[Mesa-dev] [PATCH 6/7] nouveau: make fence API independent from nouveau_screen

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_buffer.c | 37 +++ src/gallium/drivers/nouveau/nouveau_buffer.h | 2 +- src/gallium/drivers/nouveau/nouveau_fence.c | 96 +-- src/gallium/drivers/nouveau/nouveau_fence.h | 38 ++-- src/gallium

[Mesa-dev] [PATCH 0/7] Multi Context fixes for Nouveau

VDPAU) * other applications which randomly crashes related to this Karol Herbst (7): nouveau: include all compile dependencies for nouveau_context.h nouveau: extract nouveau_context functions into a new file nv50,nvc0: simplify screen.fence nouveau: access client and pushbuf from context

[Mesa-dev] [PATCH 2/7] nouveau: extract nouveau_context functions into a new file

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/Makefile.sources | 1 + src/gallium/drivers/nouveau/meson.build | 1 + src/gallium/drivers/nouveau/nouveau_context.c | 19 +++ src/gallium/drivers/nouveau/nouveau_screen.c | 18 -- 4 files

[Mesa-dev] [PATCH 1/7] nouveau: include all compile dependencies for nouveau_context.h

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_context.h | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/nouveau/nouveau_context.h b/src/gallium/drivers/nouveau/nouveau_context.h index c3bbb11bd60..38c19790ec3 100644 --- a/src/gallium/drivers

Re: [Mesa-dev] [PATCH 1/2] nv50/ir: fix use-after-free in ConstantFolding::visit

On Fri, Dec 7, 2018 at 1:58 PM Ilia Mirkin wrote: > > On Fri, Dec 7, 2018 at 3:57 AM Karol Herbst wrote: > > > > opnd() might delete the passed in instruction, but it's used through > > i->srcExists() later in visit > > > > Signed-off-by: Karol H

[Mesa-dev] [PATCH v2 1/2] nv50/ir: fix use-after-free in ConstantFolding::visit

opnd() might delete the passed in instruction, but it's used through i->srcExists() later in visit v2: use continue instead return Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_peephole.cpp | 71 +++ 1 file changed, 43 insertions(+), 28 deletions(-) d

[Mesa-dev] [PATCH 2/2] nouveau: use atomic operations for driver statistics

multiple threads can write to those at the same time Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_screen.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h b/src/gallium/drivers/nouveau

[Mesa-dev] [PATCH 1/2] nv50/ir: fix use-after-free in ConstantFolding::visit

opnd() might delete the passed in instruction, but it's used through i->srcExists() later in visit Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_peephole.cpp | 71 +++ 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/src/gallium/drivers/nouv

[Mesa-dev] [PATCH 2/2] nv50/ir: initialize relDegree staticly

this race condition is pretty harmless, but also pretty trivial to fix Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_ra.cpp| 23 +-- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src

Re: [Mesa-dev] [PATCH 2/2] nouveau: use atomic operations for driver statistics

On Mon, Dec 10, 2018 at 12:32 PM Emil Velikov wrote: > > Hi Karol, > > On Sat, 8 Dec 2018 at 17:10, Karol Herbst wrote: > > > > multiple threads can write to those at the same time > > > > Signed-off-by: Karol Herbst > Should we pick and the other two fi

[Mesa-dev] [PATCH v3] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

the new value of num_samplers Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106577 Fixes: 4d6fab245eec3880e2a59424a579851f44857ce8 "cso: don't track the number of sampler states bound" Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv50/nv50_st

Re: [Mesa-dev] [PATCH 1/2] nv50/ir: don't optimize dnz muls to add

], CONST[0][17].xyww 9: END On Sun, Nov 25, 2018 at 2:12 AM Ilia Mirkin wrote: > > Can you elaborate as to what the issue is? The dnz flag is set when we > want to make NaN -> Infinity. Do you have a concrete TGSI program that > triggers issues? > On Sat, Nov 24, 2018 at 6:04 PM K

Re: [Mesa-dev] [PATCH 2/2] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

make much of a difference what the actual value is. Sure we end up with unused but bound object, but the original change inside gallium also stopped caring about this completely. Maybe I overlooked something, though. > On Sat, Nov 24, 2018 at 6:04 PM Karol Herbst wrote: > > > > The new a

Re: [Mesa-dev] [PATCH] nv50/ir: remove dnz flag when converting MAD to ADD due to optimizations

yeah, sounds fine. I wasn't 100% sure what the dnz flag does, with the addition below: Reviewed-by: Karol Herbst diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp index 307d8762506..202faf0746a 100644 --- a/src

[Mesa-dev] [PATCH 1/2] nv50/ir: don't optimize dnz muls to add

fixes asserts with gallium nine Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [PATCH 0/2] gallium nine fixes for nouveau

know if this is the correct fix for it, but it makes sense to me reading the commit message of the gallium change. No piglit regressions and games are working again using gallium nine and nouveau. Maybe we should drop that entire num_samples handling alltogether? Karol Herbst (2): nv50/ir: don't

[Mesa-dev] [PATCH 2/2] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

umber of sampler states bound" Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv50/nv50_state.c | 13 ++--- src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 17 + 2 files changed, 7 insertions(+), 23 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv50/nv

[Mesa-dev] [PATCH 2/4] nouveau: extract nouveau_context functions into a new file

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/Makefile.sources | 1 + src/gallium/drivers/nouveau/meson.build | 1 + src/gallium/drivers/nouveau/nouveau_context.c | 19 +++ src/gallium/drivers/nouveau/nouveau_screen.c | 18 -- 4 files

[Mesa-dev] [PATCH 4/4] nouveau: access client and pushbuf from context directly

preparation for fixing our multi context issues. Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv30/nv30_context.c | 4 ++-- src/gallium/drivers/nouveau/nv30/nv30_draw.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_compute.c | 4 ++-- src/gallium/drivers/nouveau/nv50

[Mesa-dev] [PATCH 0/4] Some prep work for fixing multi context issues in Nouveau

owned by the context. Karol Herbst (4): nouveau: include all compile dependencies for nouveau_context.h nouveau: extract nouveau_context functions into a new file nv50,nvc0: simplify screen.fence nouveau: access client and pushbuf from context directly src/gallium/drivers/nouveau

[Mesa-dev] [PATCH 3/4] nv50,nvc0: simplify screen.fence

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv50/nv50_screen.c | 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_screen.h | 1 - src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 4 ++-- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 - 4 files changed, 4 insertions(+), 6

Re: [Mesa-dev] [PATCH 0/4] Some prep work for fixing multi context issues in Nouveau

On Tue, Nov 20, 2018 at 10:34 PM Ilia Mirkin wrote: > > On Tue, Nov 20, 2018 at 4:12 PM Karol Herbst wrote: > > > > On Tue, Nov 20, 2018 at 8:42 PM Ilia Mirkin wrote: > > > > > > On Tue, Nov 20, 2018 at 2:22 PM Karol Herbst wrote: > > > > > &

[Mesa-dev] [PATCH 1/4] nouveau: include all compile dependencies for nouveau_context.h

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_context.h | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/nouveau/nouveau_context.h b/src/gallium/drivers/nouveau/nouveau_context.h index c3bbb11bd60..38c19790ec3 100644 --- a/src/gallium/drivers

Re: [Mesa-dev] [PATCH 0/4] Some prep work for fixing multi context issues in Nouveau

On Tue, Nov 20, 2018 at 8:42 PM Ilia Mirkin wrote: > > On Tue, Nov 20, 2018 at 2:22 PM Karol Herbst wrote: > > > > This series cleans up some code in preparation for the real fix and contains > > cleanups we want to have regardless. > > > > The approach in so

Re: [Mesa-dev] [PATCH] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

nyway. We could improve that code in future patches though. > On Sun, Nov 25, 2018 at 10:47 AM Karol Herbst wrote: > > > > The new approach is that samplers don't get unbound even if they won't be > > used > > in a draw and we should just leave them be as well. > > >

Re: [Mesa-dev] [PATCH] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

On Mon, Nov 26, 2018 at 12:08 AM Ilia Mirkin wrote: > > On Sun, Nov 25, 2018 at 5:43 PM Karol Herbst wrote: > > > > On Sun, Nov 25, 2018 at 5:48 PM Ilia Mirkin wrote: > > > > > > Would it make sense to instead keep track of a samplers_bound[] like > >

Re: [Mesa-dev] [PATCH] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

agine. Since it's trivial to > implement, I don't really understand why we're talking about this... > On Sun, Nov 25, 2018 at 6:15 PM Karol Herbst wrote: > > > > On Mon, Nov 26, 2018 at 12:08 AM Ilia Mirkin wrote: > > > > > > On Sun, Nov 25, 2018 at 5:43 PM Kar

Re: [Mesa-dev] [PATCH] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

h > simpler. > On Sun, Nov 25, 2018 at 10:47 AM Karol Herbst wrote: > > > > The new approach is that samplers don't get unbound even if they won't be > > used > > in a draw and we should just leave them be as well. > > > > Fixes a regression in multiple windo

[Mesa-dev] [PATCH] nv50, nvc0: Fix gallium nine regression regarding sampler bindings

://bugs.freedesktop.org/show_bug.cgi?id=106577 Fixes: 4d6fab245eec3880e2a59424a579851f44857ce8 "cso: don't track the number of sampler states bound" Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nv50/nv50_state.c | 19 ++- src/gallium/drivers/no

Re: [Mesa-dev] [PATCH 14/22] nir: add legal bit_sizes to intrinsics

On Wed, Nov 21, 2018 at 10:58 PM Jason Ekstrand wrote: > > > > On Tue, Nov 13, 2018 at 9:49 AM Karol Herbst wrote: >> >> With OpenCL some system values match the address bits, but in GLSL we also >> have some system values being 64 bit. >> >> With

Re: [Mesa-dev] [PATCH 03/22] nir/spirv: initial handling of OpenCL.std extension opcodes

On Wed, Nov 21, 2018 at 2:54 AM Jason Ekstrand wrote: > > On Tue, Nov 13, 2018 at 9:48 AM Karol Herbst wrote: >> >> Not complete, mostly just adding things as I encounter them in CTS. But >> not getting far enough yet to hit most of the OpenCL.std instructions. >>

Re: [Mesa-dev] [PATCH 09/12] nir: add legal bit_sizes to intrinsics

On Mon, Jan 7, 2019 at 6:16 PM Jason Ekstrand wrote: > > On Tue, Dec 4, 2018 at 12:27 PM Karol Herbst wrote: >> >> With OpenCL some system values match the address bits, but in GLSL we also >> have some system values being 64 bit like subgroup masks. >> >>

Re: [Mesa-dev] [PATCH 11/12] nir: add support for address bit sized system values

On Mon, Jan 7, 2019 at 6:29 PM Jason Ekstrand wrote: > > > On Tue, Dec 4, 2018 at 12:27 PM Karol Herbst wrote: >> >> Signed-off-by: Karol Herbst >> --- >> src/amd/vulkan/radv_meta_buffer.c | 8 ++-- >> src/amd/vulkan/radv_meta_bufimage.c

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