int pkt_len = brw->gen >= 8 ? 4 : 3;
> + uint32_t dw1 = BRW_HW_BINDING_TABLE_ENABLE;
> + if (brw->is_haswell)
> + dw1 |= SET_FIELD(GEN7_MOCS_L3, GEN7_HW_BT_POOL_MOCS) |
> + HSW_BT_POOL_ALLOC_MUST_BE_ONE;
> + else if (brw->gen >= 8)
> +
On Tuesday, July 07, 2015 11:53:29 AM Abdiel Janulgue wrote:
> When hardware-generated binding tables are enabled, use the hw-generated
> binding table format when uploading binding table state.
>
> Normally, the CS will will just consume the binding table pointer commands
> as pipelined state. Wh
);
> gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
> + if (brw->use_resource_streamer)
> + gen7_disable_hw_binding_tables(brw);
> if (params->use_wm_prog) {
>uint32_t wm_surf_offset_renderbuffer;
>uint32_t wm_surf_offset
On Friday, July 17, 2015 09:22:26 AM Abdiel Janulgue wrote:
>
> On 07/17/2015 05:41 AM, Kenneth Graunke wrote:
>
> >>
> >> +static uint32_t
> >> +reserve_hw_bt_space(struct brw_context *brw, unsigned bytes)
> >> +{
> >> + if (brw->h
g_tables.c
> +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
> @@ -50,6 +50,33 @@ static const GLuint stage_to_bt_edit[MESA_SHADER_FRAGMENT
> + 1] = {
> _3DSTATE_BINDING_TABLE_EDIT_PS,
> };
>
> +static uint32_t
> +reserve_hw_bt_space(struct brw_context *brw, u
To fix these warnings, this patch reverts the changes made in
> commit c9dbdc0.
>
> It'll be better to add the Yf/Ys tiling selection code later, when we
> are ready to use it.
>
> Cc: Kenneth Graunke
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
Thanks Anuj...
Generated by sed; no manual changes.
Signed-off-by: Kenneth Graunke
---
We talked about doing this back in 2013, but the patches never
quite materialized. Here's the obvious sed job. Actual patch
is here:
http://cgit.freedesktop.org/~kwg/mesa/commit/?h=enumtostring
I figured I'd
st.writemask & (1 << c)) {
>
Thanks! I made a similar fix in the FS backend a long time ago;
apparently I forgot to check the vec4 backend. Good catch.
NIR probably generates a lot more SELs, so it makes sense this would
cause more trouble with that.
Reviewed-by: Kenneth Graunke
l_FragDepth)
* Source 5: [optional] Sample Mask (gl_SampleMask)
* Source 6: [required] Number of color components (as a UD immediate).
*/
Patches 1-10 are:
Reviewed-by: Kenneth Graunke
Patches 11-12 are:
Acked-by: Kenneth Graunke
> + FS_OPCODE_FB_WRITE_LOGICAL,
> FS_OPCODE_B
On Friday, June 19, 2015 03:46:51 AM Kenneth Graunke wrote:
> I made some comments, but assuming those are taken care of,
> patches 1-22 are:
>
> Reviewed-by: Kenneth Graunke
>
> I plan on reviewing the rest, but probably not tonight.
> Thanks for picking this up!
The whol
t; operation to avoid hacking on asserts (Kayden)
> v3.1: fix warnings in this patch, fix nir,
> fix tgsi
>
> Reviewed-by: Chris Forbes
> Signed-off-by: Dave Airlie
Patches 7-9 are:
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part
er value, so we always have the correct number
at each step.
Fixes new Piglit tests glsl-vs-swizzle-swizzle-lhs-[23].
Fixes ir_validate assertions in in Metro 2033 Redux.
Cc: i...@freedesktop.org
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/glsl/ir.cpp | 2 ++
1
ut it looks like we're storing them in the shader, rather than
per-context. Bug? Or am I missing something?
At this point I'm just inclined to give everything I haven't reviewed an
Acked-by: Kenneth Graunke
I don't think anybody wants to spend much more time on this, and it&#x
On Thursday, July 23, 2015 03:33:40 PM Dave Airlie wrote:
> On 23 July 2015 at 15:01, Kenneth Graunke wrote:
> > On Tuesday, July 21, 2015 03:19:25 PM Dave Airlie wrote:
> >> From: Dave Airlie
> >>
> >> This fleshes out the APIs, using the program resour
On Thursday, July 23, 2015 05:41:51 PM Dave Airlie wrote:
> From: Dave Airlie
>
> This just adds some missing pieces to nir/i965,
> it is lightly tested on my Haswell.
>
> Signed-off-by: Dave Airlie
Thanks Dave!
Reviewed-by: Kenneth Graunke
signature.asc
Description: T
On Saturday, July 18, 2015 05:34:47 PM Francisco Jerez wrote:
> Each logical variant is largely equivalent to the original opcode but
> instead of taking a single payload source it expects the arguments
> separately as individual sources, like:
>
> tex_logical dst, coordinates, shadow_c, lod, lod
alloc_strdup(shader, shader_prog->Label);
> shader->info.num_textures = num_textures;
>
Whoops. Right, this is more useful.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Sunday, October 11, 2015 04:30:13 PM Rhys Kidd wrote:
> Signed-off-by: Rhys Kidd
> ---
> README | 13 -
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/README b/README
> index e301d0e..6ed3244 100644
> --- a/README
> +++ b/README
> @@ -47,7 +47,18 @@ ST_DEBUG=pr
instructions), I decided to just make three new
opcodes.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h| 3 +++
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 +++
src/mesa/drivers/dri/i965
It's stored in bits 31:27 of g1 (along with the URB handles).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
In scalar mode, geometry shader inputs can easily take up hundreds of
registers. This makes pushing VUE entries impractical; we'll need to
resort to the pull model in some cases.
To support this, we introduce a new opcode corresponding to the "URB
Read SIMD8" message.
Signed-
hoice.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.h | 10 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 30 ++--
2 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/driver
GS doesn't have ClampVertexColor, and we don't want to go through VS
structures.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 51189a2..a67e545 100644
--- a/src/mesa/drivers/dri/i965
Tessellation shaders and SIMD8 geometry shaders may need to resort to
the pull model for inputs at times. When set, the state upload code
will tell the hardware to provide URB handles for input data.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 3 +++
src/mesa
The GS will emit a bunch of vertices, and we don't want to do an EOT
prematurely. We'll emit GS_OPCODE_THREAD_END when we want to terminate
the thread.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletio
).
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 5b93fdb..b8a5cc6 100644
--- a/src
We really ought to compute the VUE map at link time and stash it, rather
than recomputing it here, but with the mess of program structures I
wasn't sure where to put it. We can improve that later.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_nir.c
This patch introduces a brw->scalar_gs flag, similar to brw->scalar_vs,
which controls whether or not to use SIMD8 geometry shaders.
For now, we control it via a new environment variable, INTEL_SCALAR_GS.
This provides a convenient way to try it out.
Signed-off-by: Kenneth Graunke
---
sr
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 174 ++
src/mesa/drivers/dri/i965/brw_fs.h| 16 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 378 ++
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
rs/dri/i965/brw_vec4_nir.cpp | 22 +++---
> 4 files changed, 43 insertions(+), 27 deletions(-)
Thanks, Iago! This looks good to me.
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
__
Instead, print "Scalar VS" or "Scalar FS". Otherwise it's really
confusing which stage is broken.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_validate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri
support scalar mode.
>
> commit 2953c3d76178d7589947e6ea1dbd902b7b02b3d4
> Author: Kenneth Graunke
> Date: Fri Aug 14 15:15:11 2015 -0700
>
> i965/vs: Map scalar VS input locations properly; avoid tons of MOVs.
>
> Signed-off-by: Jordan Justen
> Cc: Kenneth G
On Tuesday, October 13, 2015 09:02:48 PM Jordan Justen wrote:
> On 2015-10-13 20:04:36, Kenneth Graunke wrote:
> > On Tuesday, October 13, 2015 01:44:55 PM Jordan Justen wrote:
> > > The commit shown below caused compute shaders to hit the unreachable
> > > in the
everything out to vec4
slots, similar to type_size_vec4(), but counts in scalar components,
similar to type_size_scalar().
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 52 ++
src/mesa/driver
es in
store_output intrinsics.
Not observed to fix any Piglit or dEQP tests, but does fix various
tcs-input Piglit tests on a branch that implements tessellation shaders.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
src/mesa/driver
VS, GS, and FS continue doing the same thing they did before. We can
simplify the FS code a bit because it is always scalar.
Compute shaders now assert that there are no outputs instead of doing
a loop over 0 outputs.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kenneth Graunke
On Thursday, October 15, 2015 03:17:19 PM Kenneth Graunke wrote:
> VS, GS, and FS continue doing the same thing they did before. We can
> simplify the FS code a bit because it is always scalar.
>
> Compute shaders now assert that there are no outputs instead of doing
> a loop
Marek made core Mesa call ProgramStringNotify(), which solves this
properly. The hack is no longer needed.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vs.c | 12
1 file changed, 12 deletions(-)
Thanks, Marek!
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
On Monday, October 12, 2015 02:55:32 PM Kenneth Graunke wrote:
> +void
> +fs_visitor::emit_gs_input_load(const fs_reg &dst,
> + const nir_src &vertex_src,
> + unsigned input_offset,
> +
gly long time ago):
> commit f3c6d6f1e151f6a44a76038dccebe4434038dcb1
> Author: Kenneth Graunke
> Date: Thu Nov 29 21:00:27 2012 -0800
>
> i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
>
> Cc: Kenneth Graunke
> Signed-off-by: Ben Widawsky
> ---
&g
it in patch 5 would make sense...)
With that fixed, the series is:
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signed message part.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
On Monday, October 12, 2015 02:49:03 PM Kenneth Graunke wrote:
> In the vec4 backend, we have a vec4_instruction::urb_write_flags field.
> There are many kinds of flags for SIMD4x2 messages.
>
> However, there are really only two (per-slot offset, use channel masks)
> for SIMD8 me
ol(p, BRW_MASK_DISABLE);
> - struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
> + struct brw_reg reg = stride(src1, 1, 4, 0);
> if (dispatch_width == 8) {
>brw_ADD(p, dst, src0, reg);
> } else if (dispatch
GEOMETRY_SHADER_INVOCATIONS */
> unsigned invocations;
> +
> + /** Whether or not this shader uses EndPrimitive */
> + bool uses_end_primitive;
> +
> + /** Whether or not this shader uses non-zero streams */
> + bool uses_streams;
>
> GLbitfield64 inputs_read =
> - gp->program.Base.InputsRead & ~VARYING_BIT_PRIMITIVE_ID;
> + nir->info.inputs_read & ~VARYING_BIT_PRIMITIVE_ID;
> brw_compute_vue_map(brw->intelScreen->devinfo,
> &c.input_vue_map
On Monday, October 19, 2015 02:54:56 PM Emil Velikov wrote:
> Ping on these two trivial patches ?
>
> -Emil
Oh, sorry, I thought I'd sent R-bs for these...
Both are
Reviewed-by: Kenneth Graunke
signature.asc
Description: This is a digitally signe
cted behavior.
>*str = ralloc_vasprintf(NULL, fmt, args);
> + *start = strlen(*str);
> return true;
> }
This patch is:
Reviewed-by: Kenneth Graunke
Thanks for fixing my cheesy string library :)
signature.asc
Description: This is a digitally signed message par
; - if (!reads_flag())
> - return false;
> + if (opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2)
> + return true;
>
>switch (predicate) {
>case BRW_PREDICATE_NONE:
>
Thanks, Alejandro!
Reviewed-by: Kenneth Graunke
signature.asc
Desc
The public API for the generator is brw_vec4_generate_code(); nobody
actually needs to use the class. This means we can extend it without
triggering the recompiles associated with altering brw_vec4.h.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.h | 111
vec4_generator is a class for convenience, but only exports a single
method as its public API. It makes much more sense to just export a
single function.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 6 +++---
src/mesa/drivers/dri/i965/brw_vec4.h
.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_ir_vec4.h | 3 -
src/mesa/drivers/dri/i965/brw_vec4.cpp | 86 +
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 112
We really weren't taking advantage of vec4_generator being a class.
By adding a "p" parameter to the helper methods, and "prog_data" to
ones which need binding table information, we can convert everything
to static functions.
Signed-off-by: Kenneth Graunke
---
e TCS is absent, we can't do this optimization.
Cc: Ilia Mirkin
Cc: Marek Olšák
Signed-off-by: Kenneth Graunke
---
src/glsl/linker.cpp | 16
1 file changed, 16 insertions(+)
Works for me on i965, but I haven't set up other drivers to test
them (sorry...)
diff -
programs with > 16 FS input varyings.
I think we probably just emitted extra pointless code, but probably
didn't break anything. We might also just have no tests for that.
Signed-off-by: Kenneth Graunke
Cc: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 5 +
1 file changed, 1 i
Integer varyings need to be flat qualified - all others were already.
I think we just missed this. Presumably some hardware passes this via
sideband and ignores attribute interpolation, so no one has noticed.
Signed-off-by: Kenneth Graunke
Cc: Chris Forbes
---
src/glsl/builtin_variables.cpp
varying. We have the SF override the value to 0
when the previous stage didn't actually write a value (it's actually
defined to return 0).
Signed-off-by: Kenneth Graunke
Cc: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 ++-
src/mesa/drivers/dri/i965/brw_
I changed this from COUNT to PAD in commit 268008f98c3810b9f276df985dc93ef.
Signed-off-by: Kenneth Graunke
Cc: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_compiler.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa
to
calculate a value dynamically and hook it up in the SBE packets.
Signed-off-by: Kenneth Graunke
Cc: Chris Forbes
---
src/mesa/drivers/dri/i965/brw_state.h | 3 ++-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 13 -
src/mesa/drivers/dri/i965/gen7_sf_state.c | 5 +++--
src/m
On Monday, October 26, 2015 02:10:29 PM Ilia Mirkin wrote:
> On Mon, Oct 26, 2015 at 2:03 PM, Kenneth Graunke
> wrote:
> > Integer varyings need to be flat qualified - all others were already.
> > I think we just missed this. Presumably some hardware passes this via
> &
On Monday, October 26, 2015 05:02:07 PM Ian Romanick wrote:
> On 10/26/2015 11:03 AM, Kenneth Graunke wrote:
> > Integer varyings need to be flat qualified - all others were already.
> > I think we just missed this. Presumably some hardware passes this via
> > sideband
||
> +ctx->API == API_OPENGLES) &&
> vp->program.Base.ClipDistanceArraySize == 0) {
>key->nr_userclip_plane_consts =
> _mesa_logbase2(ctx->Transform.ClipPlanesEnabled) + 1;
>
Thanks for fixing this, Ian...I looked
on and Ilia Mirkin for debugging this
and helping track down the real issue.
Cc: Topi Pohjolainen
Cc: "11.0"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92623
Tested-by: Pierre Bourdon
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_state.h | 2 +-
src/
On Tuesday, October 27, 2015 04:40:19 PM Kristian Høgsberg wrote:
> On Mon, Oct 12, 2015 at 02:55:32PM -0700, Kenneth Graunke wrote:
> > Signed-off-by: Kenneth Graunke
> > ---
> > src/mesa/drivers/dri/i965/brw_fs.cpp | 174 ++
> > src/mes
This was introduced in GLSL IR after NIR development had branched.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/glsl_to_nir.cpp | 1 +
src/glsl/nir/nir.h | 1 +
src/glsl/nir/nir_print.c | 5 +++--
3 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir
These tessellation shader related fields need plumbing through NIR.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/glsl_to_nir.cpp | 2 ++
src/glsl/nir/nir.h | 5 +
2 files changed, 7 insertions(+)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index
gl_TessLevelOuter[] and gl_TessLevelInner[] evaluation shader inputs,
which we treat as system values because they're stored specially.
(These intrinsics are only for the TES - the TCS uses output variables.)
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir.c| 17 ++---
src
On Wednesday, October 28, 2015 05:04:07 PM Ian Romanick wrote:
> On 10/28/2015 04:43 PM, Connor Abbott wrote:
> > On Wed, Oct 28, 2015 at 7:06 PM, Ian Romanick wrote:
> >> On 10/28/2015 02:32 PM, Jason Ekstrand wrote:
> >>> ---
> >>> src/glsl/nir/nir.h | 19 +++
> >>> src/glsl/ni
On Wednesday, October 28, 2015 02:58:07 PM Kristian Høgsberg wrote:
> On Wed, Oct 28, 2015 at 2:34 PM, Jason Ekstrand wrote:
> > On Wed, Oct 28, 2015 at 2:32 PM, Jason Ekstrand
> > wrote:
> >> This series adds a nir_pass datastructure and some helpers for managing
> >> optimization and lowering
On Wednesday, October 28, 2015 02:32:00 PM Jason Ekstrand wrote:
> This series adds a nir_pass datastructure and some helpers for managing
> optimization and lowering passes. I've been meaning to get around to this
> for some time. There are a couple of primary benifits to this:
>
> First, this
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_split_var_copies.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_split_var_copies.c
b/src/glsl/nir/nir_split_var_copies.c
index d2ea58a..d463f7b 100644
--- a/src/glsl/nir/nir_split_var_copies.c
+++ b/src/glsl/nir
gress appropriately. In the future, it would be easy to add shader
dumping similar to INTEL_DEBUG=optimizer by extending the macro.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_nir.c | 123
1 file changed, 53 insertions(+), 70 deletions(-)
Ideally
We can't preserve dominance or live variable information.
This also begs the question: what about globals? Metadata only exists
at the nir_function_impl level, so it would seem there is no metadata
about global variables for us to invalidate.
Signed-off-by: Kenneth Graunke
---
src/gls
Hello,
Here's my alternative suggestion to Jason's pass manager series.
First, it implements an OPT() macro in the i965 NIR backend, and
uses it for ~all passes. (Other drivers are obviously free to do likewise!)
I chose to group up some operations (such as input lowering) which
technically use
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_global_vars_to_local.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_lower_global_vars_to_local.c
b/src/glsl/nir/nir_lower_global_vars_to_local.c
index fab2366..9fa64ed 100644
--- a/src/glsl/nir
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_copy_propagate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/glsl/nir/nir_opt_copy_propagate.c
b/src/glsl/nir/nir_opt_copy_propagate.c
index 96520f8..7d8bdd7 100644
--- a/src/glsl/nir/nir_opt_copy_propagate.c
+++ b/src
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_lower_vec_to_movs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_lower_vec_to_movs.c
b/src/glsl/nir/nir_lower_vec_to_movs.c
index c08b721..736a66c 100644
--- a/src/glsl/nir/nir_lower_vec_to_movs.c
+++ b/src/glsl
tic inline, but nir.h is included
in C++, so we can't bit-or enums without lots of casting...)
Thanks to Dylan Baker for the idea.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir.h | 5 +
src/glsl/nir/nir_metadata.c | 36
s
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_remove_phis.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/nir/nir_opt_remove_phis.c
b/src/glsl/nir/nir_opt_remove_phis.c
index 5bdf7ef..66d3754 100644
--- a/src/glsl/nir/nir_opt_remove_phis.c
+++ b/src/glsl/nir
s to the normal SIMD8
> * untyped surface read message, but that's OK because unused
> * channels will be masked out.
> */
> vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst,
> - brw_message_reg(0),
> +
allocator to add interference when there's a hazard. For
my vec4 case, we can determine this by switching on opcodes. For the
SIMD16 case, we just move the existing code there.
I audited our existing virtual opcodes that generate multiple
instructions; I believe FS_OPCODE_PACK_HALF_2x1
It doesn't actually operate on variables.
---
src/glsl/Makefile.sources | 2 +-
src/glsl/nir/nir_live_variables.c | 297 --
src/glsl/nir/nir_liveness.c | 297 ++
3 files changed, 298 insertions(+), 298 deletion
This computes liveness of SSA values, not nir_variables.
Signed-off-by: Kenneth Graunke
---
src/glsl/nir/nir.h| 4 ++--
src/glsl/nir/nir_from_ssa.c | 2 +-
src/glsl/nir/nir_live_variables.c | 12 ++--
src/glsl/nir
ther than using type_size_vec4_times_4 and then dividing by 4.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_nir.c | 3 ++-
src/mesa/drivers/dri/i965/brw_shade
the
> conditional immediately below.
I suppose that works, but having a 'prev' pointer around that points to
out-of-bounds memory is a bit ugly...
How about:
struct annotation *prev = annotation->ann_count > 1 ?
&an
On Wednesday, October 21, 2015 03:58:14 PM Matt Turner wrote:
> Will allow annotations to contain error messages (indicating an
> instruction violates a rule for instance) that are printed after the
> disassembly of the block.
> ---
> src/mesa/drivers/dri/i965/intel_asm_annotation.c | 60
> ++
n(devinfo, inst);
> + } else if (devinfo->gen < 6 &&
> + brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
> + if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
> + math_function = brw_inst_math_msg_function(devinfo, inst);
> + } else
+ .gen = GEN_GE(GEN6),
> + },
> + /* Reserved 93-124 */
> + /* BRW_OPCODE_NENOP */
> + [BRW_OPCODE_NOP] = {
> + .gen = GEN_ALL,
> + },
> +};
> +
> static unsigned
> num_sources_from_inst(const struct brw_device_info *devinfo,
>
On Tuesday, November 03, 2015 10:20:26 PM Matt Turner wrote:
> On Tue, Nov 3, 2015 at 9:47 PM, Kenneth Graunke wrote:
> > On Wednesday, October 21, 2015 03:58:14 PM Matt Turner wrote:
> >> Will allow annotations to contain error messages (indicating an
> >> inst
On Wednesday, October 21, 2015 03:58:17 PM Matt Turner wrote:
> ---
> src/mesa/drivers/dri/i965/brw_eu_validate.c | 244
>
> 1 file changed, 244 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_eu_validate.c
> b/src/mesa/drivers/dri/i965/brw_eu_validate.
at's
> no reason to hold back what I've already written -- checking for null
> source would have saved three people a week or two after all.
[PATCH 1/9] ralloc: Set *start in ralloc_vasprintf_rewrite_tail() if str is
NULL.
Reviewed-by: Kenneth Graunke
[PATCH 2/9] i965: Fill
On Saturday, October 31, 2015 06:32:31 PM Connor Abbott wrote:
> Signed-off-by: Connor Abbott
> ---
> src/glsl/nir/glsl_to_nir.cpp | 700
> ---
> 1 file changed, 259 insertions(+), 441 deletions(-)
>
> diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/
On Monday, November 02, 2015 04:29:16 PM Matt Turner wrote:
[snip]
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index e980003..ed3e335 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i9
On Monday, November 02, 2015 04:29:17 PM Matt Turner wrote:
[snip]
> @@ -362,8 +362,10 @@ src_reg::equals(const src_reg &r) const
> abs == r.abs &&
> swizzle == r.swizzle &&
> !reladdr && !r.reladdr &&
> -memcmp(&fixed_hw_reg, &r.fixed_hw_reg,
> - si
On Saturday, October 24, 2015 01:07:59 PM Rob Clark wrote:
> From: Rob Clark
>
> For gallium, at least, we'll need this to manage shader's lifetimes,
> since in some cases both the driver and the state tracker will need
> to hold on to a reference for variant managing.
>
> Use nir_shader_mutable
to handle specially.
This makes it clear which intrinsics only exist in one stage, and makes
it easy to handle inputs/outputs differently for various stages.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.h | 8 +
src/mesa/drivers/dri/i965/brw_fs_nir
e on GT4, but this definitely helps
> with
> some of the failures.
>
> Cc: Kenneth Graunke
> Cc: Jordan Justen
> Cc: mesa-sta...@lists.freedesktop.org (if the original gt4 patch goes to
> stable)
> ---
>
> Sarah, you should check this on KBL.
> Cc: Sarah Sharp
&
1.0. Thanks !
>
> commit 800217a1654ab7932870b1510981f5e38712d58b
> Author: Kenneth Graunke
>
> nir: Report progress from nir_split_var_copies().
>
> (cherry picked from commit dc18b9357b553a972ea439facfbc55e376f1179f)
>
>
> commit 2cc4e973962c1d5ea0357685
From: Jason Ekstrand
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_reg.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 083c46a..c3f77c0 100644
--- a/src/mesa/drivers/dri/i965
s reusing those registers.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h | 11
src/mesa/drivers/dri/i965/brw_fs.h| 4 +++
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 1 +
src/mesa/drivers/dri/i965/brw_fs_genera
101 - 200 of 8758 matches
Mail list logo
