[Mesa-dev] [PATCH v3 04/14] nvc0: bind driver constbuf for compute on Fermi

Changes from v3: - add new validation state for COMPUTE driver constbuf Changes from v2: - always bind the driver consts even if user params come in via clover Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c

[Mesa-dev] [PATCH v3 13/14] nv50/ir: add atomics support on shared memory for Fermi

Changes from v2: - make sure the op is OP_SELP when emitting the predicate and add one assert - use bld.getSSA() for mkOp2() - add cross edge between tryLockAndSetBB and joinBB Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/codegen/nv50_ir_emit_nv

Re: [Mesa-dev] [PATCH v3 12/14] nv50/ir: make OP_SELP a compare instruction

, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: This OP_SELP insn will be used to handle compare and swap subops. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 8 src/gallium/drivers/nou

Re: [Mesa-dev] [PATCH v3 12/14] nv50/ir: make OP_SELP a compare instruction

On 02/17/2016 10:36 PM, Ilia Mirkin wrote: On Wed, Feb 17, 2016 at 4:36 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: On 02/17/2016 10:33 PM, Ilia Mirkin wrote: Fix gk110 emitter for the updated logic? (Looks like no SELP on GM107? Perhaps just not implemented yet...)

[Mesa-dev] [PATCH] nv50/ir: emit VOTE instruction

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir.h | 4 .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 24 + .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 25 ++ .../d

[Mesa-dev] [PATCH] gallium/cso: only enable compute shaders when TGSI is supported

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94186 Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/auxiliary/cso_cache/cso_context.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c

[Mesa-dev] [PATCH] nv50: do not advertise about compute shaders

Compute shaders are totally unsupported. This avoids Clover to report that OpenCL is supported on Tesla because it's a lie. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH 0/5] nvc0: comestic changes for 3D/COMPUTE

Hi there, This series only contains cosmetic changes to improve consistency between 3D and COMPUTE pipelines. Please review. Thanks! Samuel Pitoiset (5): nvc0: rename nvc0_context::dirty to nvc0_context::dirty_3d nvc0: rename NVXX_COMPUTE to NVXX_CP nvc0: prefix compute macros with _CP_

[Mesa-dev] [PATCH 2/6] nvc0: rework nvc0_compute_validate_program()

Reduce the amount of duplicated code by re-using nvc0_program_validate(). While we are at it, change the prototype to return void. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 32 ++ src/gallium/d

[Mesa-dev] [PATCH 3/6] nvc0: rename nvc0_graph_state::flushed to ::flushed_3d

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 2 +- src/gallium/drivers/nouvea

[Mesa-dev] [PATCH] nvc0/ir: add ld lock/st unlock emission on GK104

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 35 +++--- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/n

[Mesa-dev] [PATCH 6/6] nvc0: add new validation path for compute

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 44 + src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 41 +-- 2 files changed, 31 insertions(+), 54 deletions(-) diff --git a/src/g

[Mesa-dev] [PATCH 5/5] nvc0: rename 3d binding points to NVC0_BIND_3D_XXX

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 28 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 24 +-- .../drivers/nouveau/nvc0/nvc0_shader_state.c | 8 +++ src/g

[Mesa-dev] [PATCH 2/5] nvc0: rename NVXX_COMPUTE to NVXX_CP

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 96 ++--- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 28 +++ src/gallium/drivers/nouveau/nvc0/nvc0_tex.c| 6 +- src/gallium/drivers/n

[Mesa-dev] [PATCH 1/5] nvc0: rename nvc0_context::dirty to nvc0_context::dirty_3d

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 4 +- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 16 +++ src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 2 +- .../drivers/nouveau/nvc0/nvc0_shader_s

[Mesa-dev] [PATCH] nv50/ir: restore OP_SELP to be a regular instruction

Actually OP_SELP doesn't need to be a compare instruction. Instead we just need to set the NOT modifier when building the instruction. While we are at it, fix the dst register type and use a GPR. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --

[Mesa-dev] [PATCH 5/6] nvc0: rework the validation path for 3D

This will be used to rework the validation path for compute. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/Makefile.sources | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 3 -- .../drivers/nouveau/nvc0/nvc0_state_vali

[Mesa-dev] [PATCH 4/5] nvc0: rename 3d dirty flags to NVC0_NEW_3D_XXX

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 4 +- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 18 ++--- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 58 +++--- .../drivers/nouvea

[Mesa-dev] [PATCH 3/5] nvc0: prefix compute macros with _CP_ instead of _COMPUTE_

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/mme/com90c0.mme | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_macros.h | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2

[Mesa-dev] [PATCH 4/6] nvc0: introduce a flushed flag for compute validation path

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 + src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4 +

[Mesa-dev] [PATCH 0/6] nvc0: new validation path for compute

Hi, This series reworks the validation path for compute. There are no regressions for both piglit and deqp on my NVD9. I also tested MP performance counters which use a compute program to read the counters, works fine too. Please review. Samuel Pitoiset (6): nvc0: move

[Mesa-dev] [PATCH 1/6] nvc0: move nvc0_validate_global_residents() to its correct location

This function is currently only used for the compute validation path on GK104+. While we are at it, also rename it to nvc0_compute_validate_globals() and update its prototype. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_con

Re: [Mesa-dev] [PATCH v3 02/14] nvc0: bind constant buffers for compute on Fermi

On 02/21/2016 06:49 PM, Ilia Mirkin wrote: On Wed, Feb 17, 2016 at 4:27 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: Loosely based on 3D. Changs from v3: - invalidate COMPUTE CBs after validating 3D CBs because they are aliased Changes from v2: - get rid of the 's'

Re: [Mesa-dev] [PATCH 5/5] nvc0: rename 3d binding points to NVC0_BIND_3D_XXX

On 02/22/2016 12:08 AM, Ilia Mirkin wrote: On Sun, Feb 21, 2016 at 9:18 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: /* 3d bufctx (during draw_vbo, blit_3d) */ -#define NVC0_BIND_FB0 -#define NVC0_BIND_VTX 1 -#define NVC0_BIND_VTX_TMP 2 -#

Re: [Mesa-dev] [PATCH 1/6] nvc0: move nvc0_validate_global_residents() to its correct location

On 02/22/2016 12:15 AM, Ilia Mirkin wrote: Nope. This will be needed on nvc0 as well if it's to support OpenCL. I was thinking the same thing actually but I was not sure. I think we should also validate those global buffers on Fermi. On Sun, Feb 21, 2016 at 9:19 AM, Samuel Pitoiset

Re: [Mesa-dev] [PATCH 2/6] nvc0: rework nvc0_compute_validate_program()

On Sun, Feb 21, 2016 at 9:19 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: Reduce the amount of duplicated code by re-using nvc0_program_validate(). While we are at it, change the prototype to return void. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/g

Re: [Mesa-dev] [PATCH 1/3] nvc0: fix compute state initialization on GK110+

On 02/14/2016 12:41 AM, Ilia Mirkin wrote: On Sat, Feb 13, 2016 at 6:31 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: For some unknown reasons, the command 0x518, which is FIRMWARE[0x6] Please make a note that the blob calls it, along with the args passed in (usually via s

Re: [Mesa-dev] [PATCH] gallium: fix PIPE_BIND_QUERY_BUFFER - PIPE_BIND_SCANOUT overlap

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/01/2016 10:26 PM, Marek Olšák wrote: From: Marek Olšák <marek.ol...@amd.com> --- src/gallium/include/pipe/p_defines.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/include/pipe

Re: [Mesa-dev] [Nouveau] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

On 03/10/2016 05:03 PM, Pierre Moreau wrote: On 04:27 PM - Mar 10 2016, Samuel Pitoiset wrote: On 03/10/2016 04:23 PM, Ilia Mirkin wrote: On Thu, Mar 10, 2016 at 10:14 AM, Hans de Goede <hdego...@redhat.com> wrote: Add support for clover / OpenCL kernel input parameters. Sign

[Mesa-dev] [PATCH 1/6] nvc0: rework the MP counters infrastructure

This mainly improves how we define the different list of queries. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 16 +- .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c| 2 +- .../drivers/nouveau/nvc0/nvc0_query_h

[Mesa-dev] [PATCH 5/6] nvc0: add driver metrics for SM35 (GK110)

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c| 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw_metric.c b/src/gallium/drivers/nouvea

[Mesa-dev] [PATCH 6/6] nvc0: expose SM35 perf counters to AMD_performance_monitor

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c index 6

[Mesa-dev] [PATCH 3/6] nvc0: explode config of Kepler hardware SM events

This is really verbose but most of the configuration will be reused for SM35 (GK110). Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c| 555 ++--- 1 file changed, 477 insertions(+), 78 deletions(-) diff

[Mesa-dev] [PATCH 4/6] nvc0: add MP performance counters for SM35 (GK110)

Because compute support is not enabled by default for these chipsets, NVF0_COMPUTE=1 needs to be used, along with GALLIUM_HUD to enable performance counters. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- .../drivers/nouveau/nvc0/nvc0_query_hw_sm.c

[Mesa-dev] [PATCH 0/6] *nvc0: MP perf counters improvements & SM35 support

Hi, This series reworks the MP perf counters and the driver metrics infrastructure, and it adds compute-related perf counters on GK110 (SM35). This has been tested on GF119, GK104 and GK208. No regressions with the HUD and with AMD_performance_monitor. Please review, Thanks. Samuel Pitoiset (6

Re: [Mesa-dev] [PATCH] nouveau: Fix clang reserved-user-defined-literal error.

On 03/09/2016 11:27 PM, Samuel Pitoiset wrote: On 03/09/2016 09:28 PM, Vinson Lee wrote: On Wed, Mar 9, 2016 at 5:25 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: On 03/09/2016 01:46 PM, Pierre Moreau wrote: I did hit that issue as well, but I have C++11 forced on my

Re: [Mesa-dev] [PATCH 6/6] nvc0: expose SM35 perf counters to AMD_performance_monitor

On 03/10/2016 01:28 AM, Ilia Mirkin wrote: On Wed, Mar 9, 2016 at 6:23 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 6 -- 1 file changed, 4 inse

Re: [Mesa-dev] [PATCH 4/6] nvc0: add MP performance counters for SM35 (GK110)

On 03/10/2016 01:23 AM, Ilia Mirkin wrote: On Wed, Mar 9, 2016 at 6:23 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: + if (screen->base.class_3d <= NVF0_3D_CLASS && + screen->base.class_3d != NVEA_3D_CLASS) { Why? NVEA should be t

Re: [Mesa-dev] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

On 03/10/2016 04:23 PM, Ilia Mirkin wrote: On Thu, Mar 10, 2016 at 10:14 AM, Hans de Goede wrote: Add support for clover / OpenCL kernel input parameters. Signed-off-by: Hans de Goede --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp |

Re: [Mesa-dev] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

my changes but that doesn't change anything for you. I already have a patch for the nv50 bits btw, maybe it's the right time to send it? https://cgit.freedesktop.org/~hakzsam/mesa/commit/?h=compute=640d68009bcf93c1814cee0b1a12939cb85e5895 Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.

Re: [Mesa-dev] [PATCH mesa 1/3] tgsi: Fix decl.Atomic and .Shared not propagating when parsing tgsi text

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/10/2016 04:14 PM, Hans de Goede wrote: When support for decl.Atomic and .Shared was added, tgsi_build_declaration was not updated to propagate these properly. Signed-off-by: Hans de Goede <hdego...@redhat.com> ---

Re: [Mesa-dev] [PATCH mesa 3/3] nouveau: Add support for clover / OpenCL kernel input parameters

On 03/10/2016 04:43 PM, Ilia Mirkin wrote: On Thu, Mar 10, 2016 at 10:27 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: On 03/10/2016 04:23 PM, Ilia Mirkin wrote: On Thu, Mar 10, 2016 at 10:14 AM, Hans de Goede <hdego...@redhat.com> wrote: Add support for clover / O

[Mesa-dev] [PATCH 2/3] nv50/ir: make use of auxCBSlot instead of magic numbers

This avoids using magic numbers for the driver constbuf slot which is always 15 except for compute shaders on gk104+ where the slot 0 is used. For gk104+, some special compute-related values like the thread index are uploaded to screen->parm which is currently bound on c0. Signed-off-by: Sam

Re: [Mesa-dev] [PATCH] nv50: Mark compute states as dirty on context switch

I have pushed this patch on top of the compute changes for nv50. On 03/13/2016 10:11 PM, Pierre Moreau wrote: Signed-off-by: Pierre Moreau --- src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 1 + 1 file changed, 1 insertion(+) diff --git

[Mesa-dev] [PATCH 1/3] nv50, nvc0: replace resInfoCBSlot by auxCBSlot

Having two different variables for the driver constant buffer slot is confusing and really useless. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 3 +-- .../drivers/nouveau/codegen/nv50_ir_lowering_nv

Re: [Mesa-dev] [RFC mesa] nouveau: Add support for OpenCL global memory buffers

On 03/17/2016 05:07 PM, Hans de Goede wrote: Hi, On 14-03-16 21:50, Samuel Pitoiset wrote: Btw, do you need someone with commit access to push your previous series (the tgsi thing)? I can do this for you. Thanks for the offer. IIRC Ilia wanted some minor fixes there, so I'll do a v2

Re: [Mesa-dev] [RFC mesa] nouveau: Add support for OpenCL global memory buffers

On 03/14/2016 04:28 PM, Hans de Goede wrote: Hi, On 14-03-16 16:05, Ilia Mirkin wrote: There's a less hacky and more hacky way forward. The more hacky solution is to set file index to -1 or something and then not do the lowering when you see that. The less hacky solution is the one you

[Mesa-dev] [PATCH 3/5] nvc0: remove unused data in driver CB at 0x0 for Kepler

This weird thing is there since 2013 and doesn't seem to be used (according to the codegent part). I have carefully read the code to make sure this is really unused but I will double-check with piglit. This frees the first 32 bytes of the driver constant buffer. Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH 4/5] nvc0: avoid using magic numbers for the uniform_bo offsets

Instead make use of constants to improve readability. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 13 +- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 22 + src/gallium/drivers/nouvea

[Mesa-dev] [PATCH 0/5] nvc0: driver constant buffer changes

Hi, This new series improves things related to the driver constant buffer which are useful for compute shaders on gk104+. I have still not tested the series. Please review, Thanks! Samuel Pitoiset (5): nv50,nvc0: replace resInfoCBSlot by auxCBSlot nv50/ir: make use of auxCBSlot instead

[Mesa-dev] [PATCH 5/5] nvc0: shift driver constant buffer offsets by 32 bytes

The first 32 bytes of the driver constant buffer are currently unused. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouvea

[Mesa-dev] [PATCH 4/7] nv50: rename 3d binding points to NV50_BIND_3D_XXX

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_context.c| 24 +++--- src/gallium/drivers/nouveau/nv50/nv50_context.h| 20 +- .../drivers/

[Mesa-dev] [PATCH 2/7] nv50: rename NV50_COMPUTE to NV50_CP

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 90 +++--- .../drivers/nouveau/nv50/nv50_query_hw_sm.c| 10 +-- src/gallium/drivers/

[Mesa-dev] [PATCH 0/7] nv50: rework compute/3d validation path

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Hi, This is loosely based on what I did for nvc0 few weeks ago. I have not tested this series because I don't have access to a Tesla card, but this should not break anything. By the way, doing almost the same series twice is not s

[Mesa-dev] [PATCH 6/7] nv50: rework nv50_compute_validate_program()

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Reduce the amount of duplicated code by re-using nv50_program_validate(). While we are at it, change the prototype to return void. We don't check anymore if the translation fails but improving the state validation is a long process. Sign

[Mesa-dev] [PATCH 5/7] nv50: rework the validation path for 3D

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> This exposes an interface for state validation that will be also used to rework the compute validation path. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_conte

[Mesa-dev] [PATCH 7/7] nv50: add a new validation path for compute

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> This makes use of the new state validation interface to be consistent with 3d. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_compute.c | 25 + 1 file

[Mesa-dev] [PATCH 1/7] nv50: rename nv50_context::dirty to nv50_context::dirty_3d

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 2 +- src/gallium/drivers/nouveau/nv50/nv50_context.c| 10 +++--- src/gallium/drivers/nouveau/nv50/nv50_conte

[Mesa-dev] [PATCH 3/7] nv50: rename 3d dirty flags to NV50_NEW_3D_XXX

From: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nv50/nv50_compute.c| 2 +- src/gallium/drivers/nouveau/nv50/nv50_context.c| 10 +-- src/gallium/drivers/nouveau/nv50/nv50_conte

[Mesa-dev] [PATCH 1/5] nv50, nvc0: replace resInfoCBSlot by auxCBSlot

Having two different variables for the driver constant buffer slot is confusing and really useless. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 3 +-- .../drivers/nouveau/codegen/nv50_ir_lowering_nv

[Mesa-dev] [PATCH 2/5] nv50/ir: make use of auxCBSlot instead of magic numbers

This avoids using magic numbers for the driver constbuf slot which is always 15 except for compute shaders on gk104+ where the slot 0 is used. For gk104+, some special compute-related values like the thread index are uploaded to screen->parm which is currently bound on c0. Signed-off-by: Sam

Re: [Mesa-dev] [PATCH mesa v2 1/3] nouveau: codegen: Disable more old resource handling code

Series is: Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/17/2016 10:13 AM, Hans de Goede wrote: Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled / commented out some of the old resource handling code, but not all of it. Effectively a

Re: [Mesa-dev] [PATCH] nv50, nvc0: Set only NEW_CP_GLOBALS upon binding

! Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/13/2016 10:11 PM, Pierre Moreau wrote: Signed-off-by: Pierre Moreau <pierre.mor...@free.fr> --- src/gallium/drivers/nouveau/nv50/nv50_state.c | 2 +- src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 2 +- 2 file

Re: [Mesa-dev] [PATCH] nv50, nvc0: Set only NEW_CP_GLOBALS upon binding

On 03/13/2016 10:18 PM, Samuel Pitoiset wrote: This is there since ... 2013 ... but this was never really used because it's compute-related, that might explain why you are the first one to hit the issue. :-) Luckily, this doesn't affect compute shaders on Fermi because globals buffers

Re: [Mesa-dev] [PATCH mesa] clover: Fix pipe_grid_info.indirect not being initialized

On 03/14/2016 01:50 PM, Hans de Goede wrote: After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass uninitialized memory for it to launch_grid. This commit fixes this by zero-ing the entire pipe_grid_info struct when declaring it, to avoid similar

Re: [Mesa-dev] [RFC mesa] nouveau: Add support for OpenCL global memory buffers

On 03/14/2016 08:50 PM, Hans de Goede wrote: Hi, On 14-03-16 16:41, Samuel Pitoiset wrote: On 03/14/2016 04:28 PM, Hans de Goede wrote: Hi, On 14-03-16 16:05, Ilia Mirkin wrote: There's a less hacky and more hacky way forward. The more hacky solution is to set file index to -1

Re: [Mesa-dev] [Nouveau] [PATCH mesa] clover: Fix pipe_grid_info.indirect not being initialized

On 03/14/2016 09:49 PM, Francisco Jerez wrote: Samuel Pitoiset <samuel.pitoi...@gmail.com> writes: On 03/14/2016 02:29 PM, Samuel Pitoiset wrote: On 03/14/2016 02:26 PM, Hans de Goede wrote: Hi, On 14-03-16 14:01, Samuel Pitoiset wrote: On 03/14/2016 01:50 PM, Hans de Goede

Re: [Mesa-dev] [PATCH] nv50/ir: Check for valid insn instead of defs size

This seems like correct. Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 02/25/2016 02:03 AM, Pierre Moreau wrote: On Tesla cards, the first register $r0 contains the thread id; later generations use a specialised register for it. In order to prevent the register from being

Re: [Mesa-dev] [PATCH] nouveau: Fix clang reserved-user-defined-literal error.

On 03/09/2016 09:28 PM, Vinson Lee wrote: On Wed, Mar 9, 2016 at 5:25 AM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: On 03/09/2016 01:46 PM, Pierre Moreau wrote: I did hit that issue as well, but I have C++11 forced on my SPIR-V branch. I guess adding the whitespace will

Re: [Mesa-dev] [PATCH] nouveau: Fix clang reserved-user-defined-literal error.

by default. Sure, the patch looks fine, but I wonder how he did hit that issue. :-) Anyway, if this doesn't break compilation without c++11, this patch is: Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Pierre On 11:16 AM - Mar 09 2016, Samuel Pitoiset wrote: Nouveau doesn't use

Re: [Mesa-dev] [PATCH] nouveau: Fix clang reserved-user-defined-literal error.

Nouveau doesn't use c++11 except the codegen part. How do you hit that issue? Pretty sure that you forced c++11, right? I can't reproduce that compilation error with clang 3.9 btw. On 03/09/2016 09:57 AM, Vinson Lee wrote: CXX codegen/nv50_ir.lo In file included from

Re: [Mesa-dev] [PATCH] nvc0: add support for TGSI FMA ops

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/09/2016 07:06 AM, Ilia Mirkin wrote: This will allow the nouveau backend to not try and split up ops that are fused in GLSL. Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> --- src/gallium/drivers/nou

[Mesa-dev] [PATCH 2/6] nvc0: rework the driver metrics infrastructure

This follows the same design as MP perf counters. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_query.c | 10 +- .../drivers/nouveau/nvc0/nvc0_query_hw_metric.c| 296 - .../drivers/nouvea

Re: [Mesa-dev] [PATCH mesa v2 2/3] tgsi: Add support for global / private / input MEMORY

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Btw, usually when someone has reviewed the v1 we add (v1) after the Rb tag, like: Reviewed-by: XXX (v1) On 03/16/2016 09:55 AM, Hans de Goede wrote: Extend the MEMORY file support to differentiate between global, private and

Re: [Mesa-dev] [PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code

On 03/16/2016 10:23 AM, Hans de Goede wrote: Commit c3083c7082 ("nv50/ir: add support for BUFFER accesses") disabled / commented out some of the old resource handling code, but not all of it. Effectively all of it is dead already, if we ever enter the old code paths in handeLOAD / handleSTORE

Re: [Mesa-dev] [PATCH mesa v2 3/3] nouveau: codegen: Add support for clover / OpenCL kernel input parameters

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/16/2016 09:55 AM, Hans de Goede wrote: Add support for clover / OpenCL kernel input parameters. Signed-off-by: Hans de Goede <hdego...@redhat.com> Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu> --- Changes in v2

Re: [Mesa-dev] [PATCH mesa 2/6] nouveau: codegen: Slightly refactor Source::scanInstruction() dst handling

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/16/2016 10:23 AM, Hans de Goede wrote: Use the dst temp variable which was used in the TGSI_FILE_OUTPUT case everywhere. This makes the code somewhat easier to reads and helps avoiding going over 80 chars with upcoming c

Re: [Mesa-dev] [PATCH mesa 3/6] nouveau: codegen: gk110: Make emitSTORE offset handling identical to emitLOAD

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/16/2016 10:23 AM, Hans de Goede wrote: Make the store offset handling in CodeEmitterGK110::emitSTORE identical to the one in CodeEmitterGK110::emitLOAD handling. This is just a cleanup, it does not cause any functional c

Re: [Mesa-dev] [PATCH mesa v2 1/3] tgsi: Fix decl.Atomic and .Shared not propagating when parsing tgsi text

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/16/2016 09:55 AM, Hans de Goede wrote: When support for decl.Atomic and .Shared was added, tgsi_build_declaration was not updated to propagate these properly. Signed-off-by: Hans de Goede <hdego...@redhat.com> Revie

Re: [Mesa-dev] [PATCH 5/5] nvc0: shift driver constant buffer offsets by 32 bytes

The offsets are wrong in this patch... But even after fixing them I have a few number of regressions (~10 piglit tests). Anyway, these changes are not too useful for now, so I'm going to get rid of it. I'll now try with Kepler. On 03/15/2016 09:55 PM, Samuel Pitoiset wrote: The first 32

Re: [Mesa-dev] [PATCH mesa 5/6] nouveau: codegen: Add support for OpenCL global memory buffers

Could you please get rid of the cosmetic changes (eg. the switch ones)? Because this doesn't really improve readability and in my opinion these changes should be eventually done in a separate patch. Other than that, this patch is : Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

Re: [Mesa-dev] [PATCH 01/11] nv50/ir: Check for valid insn instead of def size

01/11? Where are the other patches? On 03/13/2016 02:16 PM, Pierre Moreau wrote: On Tesla cards, the first register $r0 contains the thread id; later generations use a specialised register for it. In order to prevent the register from being given to anyone, and thus lose the thread id

Re: [Mesa-dev] [PATCH] nv50: Mark compute states as dirty on context switch

Well, without a new validation path for compute on Tesla this won't change anything because nv50_state_validate() is 3d-related and it should be never called by compute. On 03/13/2016 10:11 PM, Pierre Moreau wrote: Signed-off-by: Pierre Moreau ---

Re: [Mesa-dev] [PATCH mesa v2] clover: Fix pipe_grid_info.indirect not being initialized

Thanks Hans! Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/14/2016 03:01 PM, Hans de Goede wrote: After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass uninitialized memory for it to launch_grid. This commit fixes this by ze

Re: [Mesa-dev] [PATCH mesa] clover: Fix pipe_grid_info.indirect not being initialized

On 03/14/2016 02:26 PM, Hans de Goede wrote: Hi, On 14-03-16 14:01, Samuel Pitoiset wrote: On 03/14/2016 01:50 PM, Hans de Goede wrote: After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass uninitialized memory for it to launch_grid

Re: [Mesa-dev] [PATCH mesa] clover: Fix pipe_grid_info.indirect not being initialized

On 03/14/2016 02:29 PM, Samuel Pitoiset wrote: On 03/14/2016 02:26 PM, Hans de Goede wrote: Hi, On 14-03-16 14:01, Samuel Pitoiset wrote: On 03/14/2016 01:50 PM, Hans de Goede wrote: After pipe_grid_info.indirect was introduced, clover was not modified to set it causing it to pass

Re: [Mesa-dev] [PATCH 1/3] nvc0: fix blit triangle size to fully cover FB's > 8192x8192

What about nv50? Is there the same issue? Don't you need to update nvc0_clear_buffer() accordingly? On 03/13/2016 04:07 AM, Ilia Mirkin wrote: The idea is that a single triangle will cover the whole area being drawn, allowing the blit shader to do its work. However the max fb size is

Re: [Mesa-dev] [PATCH 3/3] nv50, nvc0: handle SQRT lowering inside the driver

*mov, *rsq; ^ CC nvc0/nvc0_surface.lo This patch is: Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Tested-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> --- .../drive

Re: [Mesa-dev] [PATCH 2/3] nv50/ir: avoid folding mul + add if the mul has a dnz

This doesn't seem crazy. Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> On 03/13/2016 04:07 AM, Ilia Mirkin wrote: Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu> --- src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 ++--- 1 file changed, 2 insertions(+),

[Mesa-dev] [PATCH 1/2] tgsi: fix out of bounds access in exec_atomop()

The number of channels must be 4 for all RGBA components. Fixes: 22d129601 ("tgsi: add support for image operations to tgsi_exec. (v2.1)") Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Cc: Dave Airlie <airl...@redhat.com> --- src/gallium/auxiliary/tgsi/tgsi

[Mesa-dev] [PATCH 2/2] tgsi: silence compiler warning in fetch_sampler_unit()

The unit variable can be used uninitialized. Fixes: 24e77cb09 ("tgsi: handle indirect sampler arrays. (v2)") Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Cc: Dave Airlie <airl...@redhat.com> --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +- 1 file chan

[Mesa-dev] [PATCH] nv50/ir: do not try to attach JOIN ops to ATOM

This might result in an INVALID_OPCODE dmesg error in case a join is attached to an atomic operation. Spotted with arb_shader_image_load_store-host-mem-barrier on GK104. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/d

Re: [Mesa-dev] [PATCH] nv50/ir: do not try to attach JOIN ops to ATOM

On 04/07/2016 10:46 PM, Ilia Mirkin wrote: On Thu, Apr 7, 2016 at 4:42 PM, Samuel Pitoiset <samuel.pitoi...@gmail.com> wrote: This might result in an INVALID_OPCODE dmesg error in case a join is attached to an atomic operation. Spotted with arb_shader_image_load_store-host-mem-b

[Mesa-dev] [PATCH] trace: add missing set_shader_images()

Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/trace/tr_context.c| 39 ++ src/gallium/drivers/trace/tr_dump_state.c | 40 +++ src/gallium/drivers/trace/tr_dump_state.h | 2 ++ 3 files chang

[Mesa-dev] [RFC 00/24] nvc0: ARB_shader_image_load_store/size on GK104

ore on GK104 Samuel Pitoiset (22): nvc0: add preliminary support for images nvc0: reserve an area for surfaces info in the driver constbuf nvc0: bind images on compute shaders for Kepler nvc0: bind images on 3D shaders for Kepler nvc0: compute correct image dimensions based on the target n

[Mesa-dev] [RFC 08/24] nvc0: enable RGB10_A2UI format on GK104

No clue why this was not enabled by default before, maybe because the SULDP conversion was wrong. Anyway, this helps in fixing all rgb10_a2ui piglit tests. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 6 +++--- 1 file chan

[Mesa-dev] [RFC 03/24] nvc0: bind images on compute shaders for Kepler

instead of pipe_surface. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 5 ++- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 54 + src/gallium/d

[Mesa-dev] [RFC 01/24] nvc0: add preliminary support for images

by Ilia Mirkin. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 17 +++ src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 4 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 + src/gallium/drivers/nouvea

[Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 26 - 2 files changed, 28 insertions

[Mesa-dev] [RFC 07/24] nvc0: shift address with blocksize for image buffers

This fixes a bunch of dEQP image buffers related tests. Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com> --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/n

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