Re: [meta-intel] [PATCH 1/3] Makefile: add verbosity and debug options to Makefile

2017-02-06 Thread Todor Minchev
On Mon, 2017-02-06 at 11:06 -0800, Jianxun Zhang wrote: > Todor, > Please refer to my 2 inline comments. > > > On Feb 2, 2017, at 2:37 PM, Todor Minchev > > wrote: > > > > By default Makefile verbosity is disabled (V=0). Verbosity can be enabled by > > setting the V environment variable to any

Re: [meta-intel] [PATCH 1/3] Makefile: add verbosity and debug options to Makefile

2017-02-06 Thread Jianxun Zhang
Todor, Please refer to my 2 inline comments. > On Feb 2, 2017, at 2:37 PM, Todor Minchev > wrote: > > By default Makefile verbosity is disabled (V=0). Verbosity can be enabled by > setting the V environment variable to any value not equal to 0 (e.g V=1) > > Example: > make clean V=1; make V=1

[meta-intel] [PATCH 1/3] Makefile: add verbosity and debug options to Makefile

2017-02-02 Thread Todor Minchev
By default Makefile verbosity is disabled (V=0). Verbosity can be enabled by setting the V environment variable to any value not equal to 0 (e.g V=1) Example: make clean V=1; make V=1 A debug version of the rmc binary can be built by using the debug Makefile target. This will include debug symbol