OK - I've looked at my NixiSat schematic, and although the 5530 symbol
implies that Vdd is connected to +5V, it's actually connected to a rail
called... VDD which in turn goes directly to the input jack via a 1N4741
11V Zener and a 100R resistor, i.e. if Vin from the wall wart is truly 12V
(as
I used these for the HV IC's from Microchip. Work fine.
http://www.onsemi.com/pub_link/Collateral/MC14504B-D.PDF
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t
It's not necessary. The HV5530 is a CMOS chip, so its low and high logic
thresholds are 30% and 70% of whatever the VCC happens to be. It only needs
to be run at 12V if you want to meet the datasheet specs for maximum clock
rates (8MHz). I have never seen a nixie clock design that clocks out at
Indeed, it may be worth trying to run the clock from lower voltages, e.g. 9V or
7V instead of 12V, so the VDD-2V Vih is not so far off the mark. I think the
cascading issue mentioned above shouldn't be a problem at the likely low clock
frequency. But he mentioned a triangle wave on the data line
I don't know how the law in the US goes, but does the IP get inherited? If
the family was thinking in earning some money from this design (faulty as
it could prove to be), then releasing the plans would mean hurting
somebody..
Just my 2 cents...
On Wednesday, May 11, 2016 at 3:07:14 AM UTC-3, n
