a PonCat3 platform build on nativ linux instead of using Marvell:s
>> CPSS suite (beast).
>>
>> But have some problems regarding the network.
>>
>> We also have the DB-XC3-24G4XG development board from Marvell.
>
> I'm adding Chris Packham in Cc, who
Two typos in switchdev.txt
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Documentation/networking/switchdev.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/networking/switchdev.txt
b/Documentation/networking/switchdev.txt
Hi Gregory,
On 08/03/17 06:10, Gregory CLEMENT wrote:
> Hi Chris,
>
> On jeu., févr. 16 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
> wrote:
>
>> Shortly after I posted my last series I got access to a more recent
>> Marvell SDK which had some device
to retain a backwards compatible binding.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- none
Changes in v3:
- update commit message to indicate backwards incompatible change and
why it's OK
- retain dfx-server compatible
need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 4/6, 5/6 are split from the previous versions.
Patch 6/6 is the device tree portion of a change already in clk-next.
Chris Packham (6):
ARM: dts: Fix
need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 4/6, 5/6 and 6/6 are ported from the Marvell Linux kernel. I've tested
them on the hardware I have access to and things look pretty good.
Chris Packham (6
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give somes compatibility with the Marvell
supplied SDK.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- none
Documentation/devicetree/bi
don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 3/4 and 4/4 are ported from the Marvell Linux kernel. I've tested
them on the hardware I have access to and things look pretty good.
Chris Packham (4):
ARM: dts: armada-xp-98dx3236: combine dfx server nodes
ARM: dts
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give somes compatibility with the Marvell
supplied SDK.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Documentation/devicetree/bindings/net/marvell,prestera.tx
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
On 27/01/17 09:24, Chris Packham wrote:
> On 27/01/17 04:10, Gregory CLEMENT wrote:
>>> + internal-regs {
>
> [snip]
>
>>> +
>>> + dfx-registers {
>> node label
>>
>
> [snip]
>
>>> + switch {
On 27/01/17 04:10, Gregory CLEMENT wrote:
>> +internal-regs {
[snip]
>> +
>> +dfx-registers {
> node label
>
[snip]
>> +switch {
> node label
>
These are peers to the internal-regs, i.e. parts of the SoC with
mappable windows in the address space. Do they
On 27/01/17 04:10, Gregory CLEMENT wrote:
> Hi Chris,
>
> On ven., janv. 06 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
> wrote:
>
>> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
>> with integrated CPUs. They are simil
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v2:
- Update devicetree b
package as the switch.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update devicetree binding documentation for new compatible string
Changes in v3:
- Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a
new driver.
- Document
The assignment of rth->dst.output in vrf_rt6_create() and
vrf_rtable_create() used a hard tab before the '='. The neighboring
assignments did not. Make the assignment of rth->dst.output consistent
with the surrounding code.
Signed-off-by: Chris Packham <chris.pack...@alliedtele
Hi Florian,
On 07/31/2015 01:51 PM, Florian Fainelli wrote:
On 30/07/15 15:51, David Miller wrote:
From: David Miller da...@davemloft.net
Date: Thu, 30 Jul 2015 14:19:35 -0700 (PDT)
This looks fine, series applied, thanks.
I think your control block is too large, you'll need to rework this
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