在 2020/6/30 3:57, Raj, Ashok 写道:
> Hi Bjorn
>
>
> On Mon, Jun 29, 2020 at 02:33:16PM -0500, Bjorn Helgaas wrote:
>> [+cc Ashok, Ding, Casey]
>>
>> On Mon, Jun 29, 2020 at 12:32:44PM +0300, Aya Levin wrote:
>>> I wanted to turn on RO on the ETH driver based on
>>> pcie_relaxed_ordering_enabled(
x27;s suggestion,
remove the new ixgbe flag2 and only check the bit4 in the
PCIe Device Control register.
v3: Remove the code that clears the bits in DCA_T/RXCTRL, relaxed
ordering should be enabled by the HW when the bus allow it.
Ding Tianhong (2):
Revert commit 1a8b6d76dc5b (&qu
determine whether we should use the Relaxed
Ordering Attributes or not, so use this new way in the ixgbe driver.
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 22 --
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 19
ot;net:add one common config...") did,
so revert this commit.
Signed-off-by: Ding Tianhong
---
arch/Kconfig| 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
3 files changed, 1 insertion(
program according Alex's suggestion,
remove the new ixgbe flag2 and only check the bit4 in the
PCIe Device Control register.
v3: Remove the code that clears the bits in DCA_T/RXCTRL, relaxed
ordering should be enabled by the HW when the bus allow it.
Ding Tianhong (2):
Revert c
determine whether we should use the Relaxed
Ordering Attributes or not, so use this new way in the ixgbe driver.
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 22 --
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 19
ot;net:add one common config...") did,
so revert this commit.
Signed-off-by: Ding Tianhong
---
arch/Kconfig| 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
3 files changed, 1 insertion(
On 2017/8/18 13:04, Tantilov, Emil S wrote:
>> -Original Message-
>> From: Ding Tianhong [mailto:dingtianh...@huawei.com]
>> Sent: Thursday, August 17, 2017 5:39 PM
>> To: Tantilov, Emil S ; da...@davemloft.net;
>> Kirsher, Jeffrey T ; keesc
On 2017/8/17 22:17, Tantilov, Emil S wrote:
>> ret_val = ixgbe_start_hw_generic(hw);
>>
>> -#ifndef CONFIG_SPARC
>> -/* Disable relaxed ordering */
>> -for (i = 0; ((i < hw->mac.max_tx_queues) &&
>> - (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
>> -regval = IXGBE_R
On 2017/8/17 21:30, Thierry Reding wrote:
> On Thu, Aug 17, 2017 at 08:40:16PM +0800, Ding Tianhong wrote:
>>
>>
>> On 2017/8/17 18:51, Thierry Reding wrote:
>>> On Thu, Aug 17, 2017 at 10:25:30AM +0800, Ding Tianhong wrote:
>>>> The pci_find_pcie_
On 2017/8/17 18:51, Thierry Reding wrote:
> On Thu, Aug 17, 2017 at 10:25:30AM +0800, Ding Tianhong wrote:
>> The pci_find_pcie_root_port() would return NULL if the given
>> dev is already a Root Port, it looks like unfriendly to the
>> PCIe Root Port device, Thierry and
x27;s suggestion,
remove the new ixgbe flag2 and only check the bit4 in the
PCIe Device Control register.
Ding Tianhong (2):
Revert commit 1a8b6d76dc5b ("net:add one common config...")
net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
determine whether we should use the Relaxed
Ordering Attributes or not, so use this new way in the ixgbe driver.
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 37 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 32
ot;net:add one common config...") did,
so revert this commit.
Signed-off-by: Ding Tianhong
---
arch/Kconfig| 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
3 files changed, 1 insertion(
Root Port for a PCI
device")
Suggested-by: Thierry Reding
Suggested-by: Bjorn Helgaas
Signed-off-by: Thierry Reding
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7e2022
On 2017/8/17 1:56, David Miller wrote:
> From: Ding Tianhong
> Date: Wed, 16 Aug 2017 17:41:45 +0800
>
>> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING has been added
>> to indicate that Relaxed Ordering Attributes (RO) should not
>> be used for Transaction Layer Pa
On 2017/8/17 4:59, David Miller wrote:
> From: Bjorn Helgaas
> Date: Wed, 16 Aug 2017 15:02:37 -0500
>
>> Your fix looks right to me.
>
> Someone please submit this fix formally because this change is now in
> Linus's tree.
>
I will send it.
> Thank you.
>
> .
>
ot;net:add one common config...") did,
so revert this commit.
Signed-off-by: Ding Tianhong
---
arch/Kconfig| 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
3 files changed, 1 insertion(
could
query PCIe configuration space to determine if it can send
TLPs to Root Port with the Relaxed Ordering Attributes set.
The ixgbe driver could use this flag to determine if it can
send TLPs to Root Port with the Relaxed Ordering Attributes set.
Ding Tianhong (2):
Revert commit 1a8b6d76dc5b
to do next.
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/intel/ixgbe/ixgbe.h| 1 +
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c | 37 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 32 +++--
drivers/net/ethernet/intel/ixgbe/ixgbe_m
Root
Port already, it will return NULL and trigger the problem,
so check the highest_pcie_bridge to fix thie problem.
Fixes: a99b646afa8a ("PCI: Disable PCIe Relaxed Ordering if unsupported")
Reported-by: Eric Dumazet
Signed-off-by: Eric Dumazet
Signed-off-by: Ding Tianhong
---
d
Root
Port already, it will return NULL and trigger the problem,
so check the highest_pcie_bridge to fix thie problem.
Fixes: a99b646afa8a ("PCI: Disable PCIe Relaxed Ordering if unsupported")
Reported-by: Eric Dumazet
Signed-off-by: Eric Dumazet
Signed-off-by: Ding Tianhong
---
d
On 2017/8/15 22:03, Eric Dumazet wrote:
> On Tue, 2017-08-15 at 06:58 -0700, Eric Dumazet wrote:
>> On Mon, 2017-08-14 at 22:15 -0700, David Miller wrote:
>>> From: Ding Tianhong
>>> Date: Tue, 15 Aug 2017 11:23:22 +0800
>>>
>>>> Some devices h
make sure
the driver will not send the Relaxed Ordering TLPs to the Root Complex which
could not deal the Relaxed Ordering TLPs.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
Attribute when Upstream TLPs to the
Root Port.
Reported-and-suggested-by: Casey Leedom
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Casey Leedom
---
drivers/pci/quirks.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci
From: Casey Leedom
cxgb4vf Ethernet driver now queries PCIe configuration space to
determine if it can send TLPs to it with the Relaxed Ordering
Attribute set, just like the pf did.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet
processors has performance issue when use the Relaxed
Ordering Attribute, so disable Relaxed Ordering for these root port.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Alexander Duyck
Acked-by: Ashok Raj
---
drivers/pci/quirks.c | 62
et/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (3):
PCI: Disable PCIe Relaxed Ordering if unsupported
PCI: Disable Relaxed Ordering for some Intel processors
PCI: Disable Relaxed Ordering Attributes for AMD A110
ordering is not safe. In such cases the patch turns off the
relaxed ordering by clearing the capability for this device.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Ashok Raj
Acked-by: Alexander Duyck
Acked-by: Casey Leedom
---
drivers/pci/probe.c | 43
On 2017/8/15 1:19, Raj, Ashok wrote:
> On Mon, Aug 14, 2017 at 11:44:57PM +0800, Ding Tianhong wrote:
>> Casey reported that the AMD ARM A1100 SoC has a bug in its PCIe
>> Root Port where Upstream Transaction Layer Packets with the Relaxed
>> Ordering Attribute clear
Attribute when Upstream TLPs to the
Root Port.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Alexander Duyck
Acked-by: Ashok Raj
---
drivers/pci/quirks.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 1272f7e
laxed_ordering_supported() to
pcie_relaxed_ordering_enabled(),
and no need to check every intervening switch except the root ports, update
some commits.
Casey Leedom (2):
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
processors has performance issue when use the Relaxed
Ordering Attribute, so disable Relaxed Ordering for these root port.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Alexander Duyck
Acked-by: Ashok Raj
---
drivers/pci/quirks.c | 62
make sure
the driver will not send the Relaxed Ordering TLPs to the Root Complex which
could not deal the Relaxed Ordering TLPs.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
From: Casey Leedom
cxgb4vf Ethernet driver now queries PCIe configuration space to
determine if it can send TLPs to it with the Relaxed Ordering
Attribute set, just like the pf did.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet
ordering is not safe. In such cases the patch turns off the
relaxed ordering by clearing the capability for this device.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Ashok Raj
Acked-by: Alexander Duyck
Acked-by: Casey Leedom
---
drivers/pci/probe.c | 43
On 2017/8/9 11:25, Bjorn Helgaas wrote:
> On Tue, Aug 08, 2017 at 09:22:39PM -0500, Bjorn Helgaas wrote:
>> On Sat, Aug 05, 2017 at 03:15:11PM +0800, Ding Tianhong wrote:
>>> When bit4 is set in the PCIe Device Control register, it indicates
> After looking at the driver, I
Hi Bjorn:
On 2017/8/9 10:22, Bjorn Helgaas wrote:
> On Sat, Aug 05, 2017 at 03:15:11PM +0800, Ding Tianhong wrote:
>> When bit4 is set in the PCIe Device Control register, it indicates
>> whether the device is permitted to use relaxed ordering.
>> On some platforms using rela
On 2017/8/9 11:02, Bjorn Helgaas wrote:
> On Wed, Aug 09, 2017 at 01:40:01AM +, Casey Leedom wrote:
>> | From: Bjorn Helgaas
>> | Sent: Tuesday, August 8, 2017 4:22 PM
>> |
>> | This needs to include a link to the Intel spec
>> |
>> (https://software.intel.com/sites/default/files/managed/9
On 2017/8/7 11:47, David Miller wrote:
> From: Ding Tianhong
> Date: Sat, 5 Aug 2017 15:15:09 +0800
>
>> Some devices have problems with Transaction Layer Packets with the Relaxed
>> Ordering Attribute set. This patch set adds a new PCIe Device Flag,
>> PCI_DEV_F
From: Casey Leedom
cxgb4vf Ethernet driver now queries PCIe configuration space to
determine if it can send TLPs to it with the Relaxed Ordering
Attribute set, just like the pf did.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet
d-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Acked-by: Ashok Raj
---
drivers/pci/quirks.c | 88
include/linux/pci.h | 2 ++
2 files changed, 90 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6967c6b..5c9e1
-by: Ding Tianhong
Acked-by: Alexander Duyck
Acked-by: Ashok Raj
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 37 +
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers
th Relaxed Ordering Attribute enabled, so add the whole list Device ID
from Intel to the patch.
Casey Leedom (3):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_R
make sure
the driver will not send the Relaxed Ordering TLPs to the Root Complex which
could not deal the Relaxed Ordering TLPs.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
On 2017/8/5 5:06, Casey Leedom wrote:
> | From: Ding Tianhong
> | Sent: Thursday, August 3, 2017 6:44 AM
> |
> | diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> | index 6967c6b..1e1cdbe 100644
> | --- a/drivers/pci/quirks.c
> | +++ b/drivers/pci/quirks.c
&g
-by: Ding Tianhong
Acked-by: Alexander Duyck
Acked-by: Ashok Raj
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 37 +
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers
Leedom
Signed-off-by: Ding Tianhong
Acked-by: Ashok Raj
---
drivers/pci/quirks.c | 38 ++
include/linux/pci.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6967c6b..1e1cdbe 100644
--- a/drivers/pci
make sure
the driver will not send the Relaxed Ordering TLPs to the Root Complex which
could not deal the Relaxed Ordering TLPs.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
r cxgb4vf driver.
Make this patch set base on 4.13-rc2.
Casey Leedom (3):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
net/cxgb4vf: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (
From: Casey Leedom
cxgb4vf Ethernet driver now queries PCIe configuration space to
determine if it can send TLPs to it with the Relaxed Ordering
Attribute set, just like the pf did.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
Reviewed-by: Casey Leedom
---
drivers/net/ethernet
On 2017/8/3 17:13, Raj, Ashok wrote:
> Hi Ding
>
> patch looks good, except would reword the patch description for clarity
>
> here is my crack at it, feel free to use.
>
> On Thu, Jul 13, 2017 at 10:21:31PM +0800, Ding Tianhong wrote:
>> The PCIe Device Contro
>
> Acked-by: Ashok Raj
>
> On Thu, Jul 13, 2017 at 10:21:30PM +0800, Ding Tianhong wrote:
>> From: Casey Leedom
>
Thanks, Ashok. :)
Regards
Ding
>
>>
>> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
>> Ordering Attribute s
On 2017/7/28 1:49, Alexander Duyck wrote:
> On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong
> wrote:
>>
>>
>> On 2017/7/27 2:26, Casey Leedom wrote:
>>> By the way Ding, two issues:
>>>
>>> 1. Did we ever get any acknowledgement from either
On 2017/7/28 2:42, Raj, Ashok wrote:
> Hi Casey
>
>> | Still no Intel and AMD guys has ack this, this is what I am worried about,
>> | should I ping some man again ?
>
>
> I can ack the patch set for Intel specific changes. Now that the doc is made
> public :-).
>
Good, Thanks. :)
> Can you
On 2017/7/28 1:44, Casey Leedom wrote:
> | From: Ding Tianhong
> | Sent: Wednesday, July 26, 2017 6:01 PM
> |
> | On 2017/7/27 3:05, Casey Leedom wrote:
> | >
> | > Ding, send me a note if you'd like me to work that [cxgb4vf patch] up
> | > for you.
> |
>
On 2017/7/27 2:26, Casey Leedom wrote:
> By the way Ding, two issues:
>
> 1. Did we ever get any acknowledgement from either Intel or AMD
> on this patch? I know that we can't ensure that, but it sure would
> be nice since the PCI Quirks that we're putting in affect their
> produ
On 2017/7/27 3:05, Casey Leedom wrote:
> | From: Alexander Duyck
> | Sent: Wednesday, July 26, 2017 11:44 AM
> |
> | On Jul 26, 2017 11:26 AM, "Casey Leedom" wrote:
> | |
> | | I think that the patch will need to be extended to modify
> | | drivers/pci.c/iov.c:sriov_enable() to explici
On 2017/7/24 9:09, Ding Tianhong wrote:
>
>
> On 2017/7/24 1:03, Cong Wang wrote:
>> On Sun, Jul 23, 2017 at 5:48 AM, liujian (CE) wrote:
>>> Hi
>>>
>>> I find it caused by below steps:
>>> 1. set tp_version to TPACKET_V3 and req->tp_blo
On 2017/7/24 1:03, Cong Wang wrote:
> On Sun, Jul 23, 2017 at 5:48 AM, liujian (CE) wrote:
>> Hi
>>
>> I find it caused by below steps:
>> 1. set tp_version to TPACKET_V3 and req->tp_block_nr to 1
>> 2. set tp_block_nr to 0
>> Then pg_vec was freed, and we did not delete the timer?
>
> Thanks f
On 2017/7/23 3:02, Cong Wang wrote:
> Hello,
>
> On Sat, Jul 22, 2017 at 2:55 AM, liujian (CE) wrote:
>> I also hit this issue with trinity test:
>>
>> The call trace:
>> [exception RIP: prb_retire_rx_blk_timer_expired+70]
>> RIP: 81633be6 RSP: 8801bec03dc0 RFLAGS: 00010246
Hi Sinan, Bjorn:
On 2017/7/14 21:54, Sinan Kaya wrote:
> On 7/13/2017 9:26 PM, Ding Tianhong wrote:
>> There is no code to enable the PCIe Relaxed Ordering bit in the
>> configuration space,
>> it is only be enable by default according to the PCIe Standard
>> Specifi
Hi Casey, Alexander:
Thanks for the great efforts from both of you, It looks like we have reached a
consensus finally,
could you please add a confirmation message just like Reviewed-by or something
else, thanks. :)
Ding
On 2017/7/14 2:44, Casey Leedom wrote:
> Yeah, I think this works for no
On 2017/7/14 5:09, Sinan Kaya wrote:
> On 7/13/2017 10:21 AM, Ding Tianhong wrote:
>> static void pci_configure_relaxed_ordering(struct pci_dev *dev)
>> +{
>> +/* We should not alter the relaxed ordering bit for the VF */
>> +if (dev->is_virtfn)
>> +
Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/pci/quirks.c | 38
ause we are probably running in a guest machine.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 37 +
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c
ene, but we agree to leave this problem until we really trigger it.
Make this patch set base on 4.12 release version.
Casey Leedom (2):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (1):
P
make sure
the driver will not send the Relaxed Ordering TLPs to the Root Complex which
could not deal the Relaxed Ordering TLPs.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 23
On 2017/7/13 8:52, Casey Leedom wrote:
> Sorry again for the delay. This time at least partially caused by a
> Chelsio-internal Customer Support request to simply disable Relaxed Ordering
> entirely due to the performance issues with our 100Gb/s product and
> relatively recent Intel Root Co
On 2017/7/11 8:01, Casey Leedom wrote:
>
> Hey Alexander,
>
> Okay, I understand your point regarding the "most likely scenario" being
> TLPs directed upstream to the Root Complex. But I'd still like to make sure
> that we have an agreed upon API/methodology for doing Peer-to-Peer with
> Rel
Hi Casey:
On 2017/7/8 10:04, Casey Leedom wrote:
> Okay, thanks for the note Alexander.I'll have to look more closely
> at
> the patch on Monday and try it out on one of the targeted systems to verify
> the semantics you describe.
>
All the modification is only clearing the device's D
On 2017/7/7 1:17, Bjorn Helgaas wrote:
> On Thu, Jul 06, 2017 at 08:58:51PM +0800, Ding Tianhong wrote:
>> Hi Bjorn:
>>
>> Could you please give some feedback about this patchset, it looks like no
>> more comments for more than a week,
>> thanks. :)
>
&g
Hi Bjorn:
Could you please give some feedback about this patchset, it looks like no more
comments for more than a week,
thanks. :)
Ding
On 2017/6/29 13:47, Ding Tianhong wrote:
> ping
>
> On 2017/6/22 20:15, Ding Tianhong wrote:
>> Some devices have problems with Transactio
ping
On 2017/6/22 20:15, Ding Tianhong wrote:
> Some devices have problems with Transaction Layer Packets with the Relaxed
> Ordering Attribute set. This patch set adds a new PCIe Device Flag,
> PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
> devices
ause we are probably running in a guest machine.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 37 +
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (1):
PCI: Enable PCIe Relaxed Ordering if supported
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 ++
drivers/net/ethernet
Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/pci/quirks.c | 38
From: Casey Leedom
cxgb4 Ethernet driver now queries PCIe configuration space to determine
if it can send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net
On 2017/6/22 2:28, Alexander Duyck wrote:
> On Sun, Jun 18, 2017 at 11:53 PM, Ding Tianhong
> wrote:
>> From: Casey Leedom
>>
>> cxgb4 Ethernet driver now queries PCIe configuration space to determine
>> if it can send TLPs to it with the Relaxed Ordering Attr
From: Casey Leedom
cxgb4 Ethernet driver now queries PCIe configuration space to determine
if it can send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net
ause we are probably running in a guest machine.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 37 +
include/linux/pci.h | 2 ++
3 files changed, 68 insertions(+)
diff --git a/drivers/pci/pci.c
which only return the bool
value, and add the check for VF device.
Make this patch set base on 4.12-rc5.
Casey Leedom (2):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (1):
PCI:
Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/pci/quirks.c | 38
On 2017/6/16 22:39, Alexander Duyck wrote:
> On Thu, Jun 15, 2017 at 6:10 PM, Ding Tianhong
> wrote:
>>
>>
>> On 2017/6/13 5:28, Alexander Duyck wrote:
>>> On Mon, Jun 12, 2017 at 4:05 AM, Ding Tianhong
>>> wrote:
>> ...
>>>>
On 2017/6/13 5:28, Alexander Duyck wrote:
> On Mon, Jun 12, 2017 at 4:05 AM, Ding Tianhong
> wrote:
...
>> /**
>> + * pcie_clear_relaxed_ordering - clear PCI Express relaxed ordering bit
>> + * @dev: PCI device to query
>> + *
>> + * If possible cl
Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Ding Tianhong (1):
PCI: Enable PCIe Relaxed Ordering if supported
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +
From: Casey Leedom
cxgb4 Ethernet driver now queries PCIe configuration space to determine
if it can send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net
ause we are probably running in a guest machine.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 32
drivers/pci/probe.c | 41 +
include/linux/pci.h | 2 ++
3 files changed, 75 insertions(+)
diff --git a/drivers/pci
Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/pci/quirks.c | 38
On 2017/6/8 7:24, Alexander Duyck wrote:
> On Wed, Jun 7, 2017 at 2:16 AM, Ding Tianhong wrote:
>> From: Casey Leedom
>>
>> cxgb4 Ethernet driver now queries Root Complex Port to determine if it can
>> send TLPs to it with the Relaxed Ordering Attribute set.
>&g
Hi John:
Thanks for the reviewing, I will fix it in next version.
Ding
On 2017/6/8 1:55, John Garry wrote:
> On 07/06/2017 10:16, Ding Tianhong wrote:
>
> Hi Ding,
>
> A few general style comments:
>
>> The PCIe Device Control Register use the bit 4 to indicate that
From: Casey Leedom
cxgb4 Ethernet driver now queries Root Complex Port to determine if it can
send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
ause we are probably running in a guest.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 29 +
drivers/pci/probe.c | 43 +++
include/linux/pci.h | 2 ++
3 files changed, 74 insertions(+)
diff --git a/drivers/pci/pci.c
doesn't exist or isn't
the PCIe device, we shouldn't do anything and skip updating relaxed ordering
because we are probably running in a guest.
Casey Leedom (2):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLA
Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/pci/quirks.c | 38
On 2017/6/6 8:28, Alexander Duyck wrote:
> On Mon, Jun 5, 2017 at 6:33 AM, Ding Tianhong wrote:
>>
>>
>> On 2017/6/4 2:19, Alexander Duyck wrote:
>>> On Fri, Jun 2, 2017 at 9:04 PM, Ding Tianhong
>>> wrote:
>>>> The PCIe Device Control Regis
On 2017/6/4 2:19, Alexander Duyck wrote:
> On Fri, Jun 2, 2017 at 9:04 PM, Ding Tianhong wrote:
>> The PCIe Device Control Register use the bit 4 to indicate that
>> whether the device is permitted to enable relaxed ordering or not.
>> But relaxed ordering is not safe fo
On 2017/6/4 2:19, Alexander Duyck wrote:
> On Fri, Jun 2, 2017 at 9:04 PM, Ding Tianhong wrote:
>> The PCIe Device Control Register use the bit 4 to indicate that
>> whether the device is permitted to enable relaxed ordering or not.
>> But relaxed ordering is not safe fo
by default.
If a platform support relaxed ordering but does not enable it by
default, enable it in the PCIe configuration. This allows some device
to send TLPs with the relaxed ordering attributes set, which may
improve the performance.
Signed-off-by: Ding Tianhong
---
drivers/pci/pci.c | 42
From: Casey Leedom
cxgb4 Ethernet driver now queries Root Complex Port to determine if it can
send TLPs to it with the Relaxed Ordering Attribute set.
Signed-off-by: Casey Leedom
Signed-off-by: Ding Tianhong
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet
1 - 100 of 169 matches
Mail list logo
