Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
more need to use the DMA API). Thanks to this, it is
possible to use cache contrary to the access of the rx descriptor member.
The change is done in the swbm path only because the hwbm uses the cookie
field, this also means that currently the hwbm is not usable in 64-bits.
Signed-off-by: Gregory
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
by patch 4.
In patch 5 the dt support is added.
Beside Armada 37xx, the series have been tested on Armada XP and
Armada 38x (with Hardware Buffer Management and with Software Buffer
Managment).
Thanks,
Gregory
Gregory CLEMENT (3):
net: mvneta: Use cacheable memory to store the rx buffer
recommend using READ_ONCE()/WRITE_ONCE()
> to access the descriptor fields, to ensure the compiler doesn't
> add extra references as well as to annotate the expensive
> operations.
>
> Arnd
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Jisheng, Arnd,
Thanks for your feedback.
On mer., nov. 23 2016, Arnd Bergmann wrote:
> On Wednesday, November 23, 2016 5:53:41 PM CET Jisheng Zhang wrote:
>> On Tue, 22 Nov 2016 22:04:12 +0100 Arnd Bergmann wrote:
>>
>> > On Tuesday, November 22, 2016 5:48:4
Add neta nodes for network support both in device tree for the SoC and
the board.
Signed-off-by: Gregory CLEMENT
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 23 +++
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 23 +++
2 files changed, 46
ion depend on precpu interrupt.
[gregory.clem...@free-electrons.com: extract from a larger patch, replace
some ifdef and port to net-next for v4.10]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
.../bindings/net/marvell-armada-370-neta.txt | 7 +-
drivers/net/ethe
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
From: Marcin Wojtas
Prepare the mvneta driver in order to be usable on the 64 bits platform
such as the Armada 3700.
[gregory.clem...@free-electrons.com]: this patch was extract from a larger
one to ease review and maintenance.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
related to the Armada
3700 SoC. The main one being the used of shared interrupt instead of
the private ones. It has been addressed in the 3rd patch.
Not all the feature supported on the older Soc have been ported yet
for this new SoC.
Gregory CLEMENT (2):
net: mvneta: Only disable mvneta_bm for 64
Hi David,
On mar., nov. 22 2016, David Miller wrote:
> From: Gregory CLEMENT
> Date: Tue, 22 Nov 2016 17:00:37 +0100
>
>> Actually only the mvneta_bm support is not 64-bits compatible.
>> The mvneta code itself can run on 64-bits architecture.
>>
>> Signed-o
Hi,
On mar., nov. 22 2016, Gregory CLEMENT
wrote:
> Actually only the mvneta_bm support is not 64-bits compatible.
> The mvneta code itself can run on 64-bits architecture.
I have just realized that my topic prefix was wrong (net-next was
missing), I am send a new email with the c
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
Actually only the mvneta_bm support is not 64-bits compatible.
The mvneta code itself can run on 64-bits architecture.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell
-81,6 +82,7 @@ config MVPP2
> tristate "Marvell Armada 375 network interface support"
> depends on MACH_ARMADA_375 || COMPILE_TEST
> depends on HAS_DMA
> + depends on !64BIT
> select MVMDIO
> ---help---
> This driver supp
; +u8 *attr)
> +{
> + return -EINVAL;
> +}
> +#endif /* CONFIG_MVEBU_MBUS */
>
> #endif /* __LINUX_MBUS_H */
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
bstract away some
> of the Kconfig built-in and module enable details.
>
> Signed-off-by: Javier Martinez Canillas
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
>
> drivers/net/ethernet/marvell/mvneta_bm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Hi,
these two patches fix spinlock related issues introduced in v4.6. They
have been reported by Russell King and Jean-Jacques Hiblot.
Thanks to them,
Gregory
Gregory CLEMENT (2):
net: mvneta: Fix lacking spinlock initialization
net: hwbm: Fix unbalanced spinlock in error case
drivers
[]
(kernel_init_freeable+0x15c/0x1fc)
[] (kernel_init_freeable) from [] (kernel_init+0x8/0x114)
[] (kernel_init) from [] (ret_from_fork+0x14/0x24)
Fixes: baa11ebc0c76 ("net: mvneta: Use the new hwbm framework")
Reported-by: Russell King
Cc:
Signed-off-by: Gregory CLEMENT
---
drivers/ne
When hwbm_pool_add exited in error the spinlock was not released. This
patch fixes this issue.
Fixes: 8cb2d8bf57e6 ("net: add a hardware buffer management helper API")
Reported-by: Jean-Jacques Hiblot
Cc:
Signed-off-by: Gregory CLEMENT
---
net/core/hwbm.c | 3 +++
1 file changed, 3
gt; Fixes: 019ded3aa7c9 ("net: mvneta: bm: clarify dependencies")
It looks ok for me.
Acked-by: Gregory CLEMENT
Thanks,
Gregory
> ---
> drivers/net/ethernet/marvell/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/mar
config
> +++ b/drivers/net/ethernet/marvell/Kconfig
> @@ -42,7 +42,7 @@ config MVMDIO
>
> config MVNETA_BM_ENABLE
> tristate "Marvell Armada 38x/XP network interface BM support"
> - depends on MVNETA
> + depends on MVNETA && !64BIT
> ---help---
> This driver supports auxiliary block of the network
> interface units in the Marvell ARMADA XP and ARMADA 38x SoC
> --
> 2.8.0.rc3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Arnd,
On mar., mars 29 2016, Arnd Bergmann wrote:
> On Tuesday 29 March 2016 18:04:47 Gregory CLEMENT wrote:
>>
>> What is the status of this patch?
>>
>> Do you plan to send a second version with the title fixed as suggested
>> by Joe Perches?
>>
info(phys_addr_t phyaddr, u8
> *target, u8 *attr)
> }
> }
>
> - pr_err("invalid dram address 0x%x\n", phyaddr);
> + pr_err("invalid dram address %pa\n", &phyaddr);
> return -EINVAL;
> }
> EXPORT_SYMBOL_GPL(m
800
> - MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
> - MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
> + MBUS_ID(0x01, 0x2f) 0 0 0xe800 0x800
> + MBUS_ID(0x09, 0x09) 0 0 0xf110 0x1
> - MBUS_ID(0x09, 0x05) 0 0 0xf111 0x1>;
> ++ MBUS_ID(0x09, 0x05) 0 0 0xf111 0x1
> + MBUS_ID(0x0c, 0x04) 0 0 0xd120 0x10>;
>
> devbus-bootcs {
> status = "okay";
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Arnd,
I forgot to add you in CC for this patch.
What is your opinion about it?
Gregory
On lun., mars 14 2016, Gregory CLEMENT
wrote:
> From: Marcin Wojtas
>
> Some SRAM users may require non-bufferable access to the memory, which is
> impossible, because devm_ioremap_wc()
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp.dtsi | 19
, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
ry.clem...@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Acked-by: Russell King
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts | 6
Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
b/arch
orts
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Tested-by: Sebastian Careba
Signed-off-by: Gregory CLEMENT
From: Marcin Wojtas
Some SRAM users may require non-bufferable access to the memory, which is
impossible, because devm_ioremap_wc() is used for setting sram->virt_base.
This commit adds optional flag 'no-memory-wc', which allow to choose remap
method, using DT property. Documentation is updated
Now that the hardware buffer management framework had been introduced,
let's use it.
Tested-by: Sebastian Careba
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 18 +++--
drivers/net/ethernet/marvell/mvneta
d
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang
Signed-off-by: Gregory CLEMENT
---
drivers/bus/mvebu-mbus.c
patches.
In order to ease the test the branch mvneta-BM-framework-v6 is
available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory
Gregory CLEMENT (3):
ARM: dts: armada-xp-openblocks-ax3-4: Add BM support
net: add a hardware buffer management helper API
net: mvneta: U
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 19
vated CONFIG_DEBUG_ATOMIC_SLEEP. Actually, in mvneta_stop() we only
need to protect the is_stopped flagged, indeed the code of the notifier
for CPU online is protected by the same spinlock, so when we get the
lock, the notifer work is done.
Reported-by: Patrick Uiterwijk
Signed-off-by: Gregory CL
quot;net: mvneta: driver for Marvell Armada 370/XP
network unit")
Cc: sta...@vger.kernel.org
Signed-off-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvel
From: Dmitri Epshtein
Some literal values are actually already defined by macros, so let's use
them.
[gregory.clem...@free-electrons.com: split intial commit in two
individual changes]
Signed-off-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.
numbers by existing macros
Gregory CLEMENT (1):
net: mvneta: Fix spinlock usage
drivers/net/ethernet/marvell/mvneta.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
--
2.5.0
From: Dmitri Epshtein
This commit corrects error printing when shutting down the port.
[gregory.clem...@free-electrons.com: split initial commit in two
individual changes]
Signed-off-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++--
1 file
gt; case CPU_ONLINE:
> case CPU_ONLINE_FROZEN:
> + case CPU_DOWN_FAILED:
> + case CPU_DOWN_FAILED_FROZEN:
> spin_lock(&pp->lock);
> /* Configuring the driver for a new CPU while the
>* driver is stopping is racy,
uot;
- Removed the patch "ARM: mvebu: enable SRAM support in
mvebu_v7_defconfig" of this series and already applied it
- Modified the order of the patches.
In order to ease the test the branch mvneta-BM-framework-v5 is
available at g...@github.com:MISL-EBU-System-SW/mainline-publ
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 18 +++--
drivers/net/ethernet/marvell/mvneta_bm.c
orts
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas
ry.clem...@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
Acked-by: Russell King
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts | 6
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Signed-off-by: Gregory CLEMENT
---
include/net/hwbm.h | 28
Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
b/arch
From: Marcin Wojtas
Some SRAM users may require non-bufferable access to the memory, which is
impossible, because devm_ioremap_wc() is used for setting sram->virt_base.
This commit adds optional flag 'no-memory-wc', which allow to choose remap
method, using DT property. Documentation is updated
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp.dtsi | 19
, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
d
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang
Signed-off-by: Gregory CLEMENT
---
drivers/bus/mvebu-mbus.c
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 19
Hi Jisheng,
On mer., mars 09 2016, Jisheng Zhang wrote:
> Dear Gregory,
>
> On Tue, 8 Mar 2016 13:57:04 +0100 Gregory CLEMENT wrote:
>
>> In the previous patch, the spinlock was not initialized. While it didn't
>> cause any trouble yet it could be a problem to use
quot;net: mvneta: driver for Marvell Armada 370/XP
network unit")
Cc: sta...@vger.kernel.org
Signed-off-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvel
From: Dmitri Epshtein
This commit corrects error printing when shutting down the port. Also
magic numbers are replaced by existing macros.
Signed-off-by: Dmitri Epshtein
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 8
1 file changed, 4 insertions(+), 4
Epshtein (2):
net: mvneta: enable change MAC address when interface is up
net: mvneta: fix error messages in mvneta_port_down function
Gregory CLEMENT (1):
net: mvneta: Fix spinlock usage
drivers/net/ethernet/marvell/mvneta.c | 21 +++--
1 file changed, 11 insertions(+), 10
vated CONFIG_DEBUG_ATOMIC_SLEEP. Actually, in mvneta_stop() we only
need to protect the is_stopped flagged, indeed the code of the notifier
for CPU online is protected by the same spinlock, so when we get the
lock, the notifer work is done.
Reported-by: Patrick Uiterwijk
Signed-off-by: Gregory CL
pool->buf_num) < bm_pool->buf_num) {
>
> What is a point of this condition? How possibly after checking if
> capacity of pool is not exceeded, this one would ever be true?
see http://thread.gmane.org/gmane.linux.kernel/2125152/focus=2137421
this test is here to ensure that (buf_num + bm_pool->buf_nu doesn't
wrap.
Thanks,
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi,
On sam., mars 05 2016, Gregory CLEMENT
wrote:
> This is a third version of an API set for HW Buffer management that I
Please ignore this version.
Being able to select the HWBM support though the kernel configuration
was not as trivial as I initially thought. Fortunately, it was quic
Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
b/arch
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 18 +++
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp.dtsi | 18 +++
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 16 ++--
drivers/net/ethernet/marvell/mvneta_bm.c
d
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang
Signed-off-by: Gregory CLEMENT
---
drivers/bus/mvebu-mbus.c
, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
ry.clem...@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts | 6 ++
arch/arm/boot/dts/armada
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Signed-off-by: Gregory CLEMENT
---
include/net/hwbm.h | 26
orts
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas
u_v7_defconfig" of this series and already applied it
- Modified the order of the patches.
In order to ease the test the branch mvneta-BM-framework-v4 is
available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory
Gregory CLEMENT (3):
ARM: dts: armada-xp-openblocks-ax3
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Signed-off-by: Gregory CLEMENT
---
include/net/hwbm.h | 21
, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
ry.clem...@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts | 6 ++
arch/arm/boot/dts/armada
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 38 +++--
drivers/net/ethernet/marvell/mvneta_bm.c
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp.dtsi | 18 +++
d
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang
Signed-off-by: Gregory CLEMENT
---
drivers/bus/mvebu-mbus.c
orts
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 18 +++
vneta-BM-framework-v3 is
available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory
Gregory CLEMENT (3):
ARM: dts: armada-xp-openblocks-ax3-4: Add BM support
net: add a hardware buffer management helper API
net: mvneta: Use the new hwbm framework
Marcin Wojtas (
Allow Openblock AX3 using hardware buffer management with mvneta.
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
b/arch
Hi Willy,
On mer., févr. 17 2016, Willy Tarreau wrote:
> Hi Gregory,
>
> On Tue, Feb 16, 2016 at 04:33:35PM +0100, Gregory CLEMENT wrote:
>> Hello,
>>
>> A few weeks ago I sent a proposal for a API set for HW Buffer
>> management, to have a better view o
Hi David,
On jeu., janv. 14 2016, David Laight wrote:
> From: Gregory CLEMENT
>> Sent: 12 January 2016 19:11
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/bus/mvebu-mbus.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> di
, each port is
supposed to use single pool for all kind of packets.
Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-xp.dtsi | 18 +++
buffer
pointer ring residing in DRAM.
Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-38x.dtsi | 18 +++
d
PnC configuration.
[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]
Signed-off-by: Marcin Wojtas
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang
Signed-off-by: Gregory CLEMENT
---
drivers/bus/mvebu-mbus.c
This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.
Signed-off-by: Gregory CLEMENT
---
include/net/hwbm.h | 21
orts
This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.
[gregory.clem...@free-electrons.com: removed the suspend/resume part]
Signed-off-by: Marcin Wojtas
Now that the hardware buffer management framework had been introduced,
let's use it.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/Kconfig | 1 +
drivers/net/ethernet/marvell/mvneta.c| 45 +++---
drivers/net/ethernet/marvell/mvneta_bm.c
ry.clem...@free-electrons.com: add suppport for the ClearFog board]
Signed-off-by: Marcin Wojtas
Signed-off-by: Gregory CLEMENT
---
arch/arm/boot/dts/armada-385-db-ap.dts | 20 +++-
arch/arm/boot/dts/armada-388-clearfog.dts | 6 ++
arch/arm/boot/dts/armada
better if
you merge it in the same time as the 3 other ones.
Thanks,
Gregory
Gregory CLEMENT (2):
net: add a hardware buffer management helper API
net: mvneta: Use the new hwbm framework
Marcin Wojtas (6):
ARM: dts: armada-38x: add buffer manager nodes
ARM: dts: armada-38x: enable buffer
MTD_M25P80=y
> CONFIG_MTD_NAND=y
> CONFIG_MTD_NAND_PXA3xx=y
> CONFIG_MTD_SPI_NOR=y
> +CONFIG_SRAM=y
> CONFIG_EEPROM_AT24=y
> CONFIG_BLK_DEV_SD=y
> CONFIG_ATA=y
> --
> 1.8.3.1
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
/* Refill processing */
>> - err = mvneta_rx_refill(pp, rx_desc);
>> + err = bm_in_use ? mvneta_bm_pool_refill(pp->bm_priv,
>> bm_pool) :
>> + mvneta_rx_refill(pp, rx_desc);
>> if (err
Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and disabled at initialization, so
there is no point to disable them first.
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 8
1 file
s: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethern
ensures
that all the calls will be done all at once.
Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese
Suggested-by: Jisheng Zhang
Suggested-by: Russell King
Signed-off-by: Gregory CLEMENT
---
drivers/net/ethernet/marvell/mvneta.c | 8 +++---
in the comments. Pointed by Sergei Shtylyov
- Add a new patch fixing the CPU choice in mvneta_percpu_elect
- Use lock in last patch to prevent remaining race condition. Pointed
by Jisheng
Gregory CLEMENT (7):
net: mvneta: Fix for_each_present_cpu usage
net: mvneta: Fix the CPU cho
Instead of using a for_each_* loop in which we just call the
smp_call_function_single macro, it is more simple to directly use the
on_each_cpu macro. Moreover, this macro ensures that the calls will be
done all at once.
Suggested-by: Russell King
Signed-off-by: Gregory CLEMENT
---
drivers/net
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