On Tue, Apr 13, 2021 at 1:45 AM Andrew Lunn wrote:
[...]
> > > and a few people have forked it and modified it for other DSA
> > > switches. At some point we might want to try to merge the forks back
> > > together so we have one tool to dump any switch.
> > actually I was wondering if there is so
Hi Andrew,
On Mon, Apr 12, 2021 at 1:16 AM Andrew Lunn wrote:
>
> On Sun, Apr 11, 2021 at 10:55:11PM +0200, Martin Blumenstingl wrote:
> > Add support for .get_regs_len and .get_regs so it is easier to find out
> > about the state of the ports on the GSWIP hardware. For this w
auto polling mechanism). Other global and per-port
registers which are also considered useful are included as well.
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 83 ++
1 file changed, 83 insertions(+)
diff --git a
Hi Sasha,
On Sun, Apr 11, 2021 at 6:48 PM Sasha Levin wrote:
>
> On Sun, Apr 11, 2021 at 12:23:42PM +0200, Martin Blumenstingl wrote:
> >Hello,
> >
> >This backports two patches (which could not be backported automatically
> >because the gswip_phylink_mac_link_up
igned-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Greg Kroah-Hartman
[ Updated after the upstream commit 3e9005be8 required some changes
for Linux 5.4 ]
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 19 +++
dsa: lantiq_gswip: Let GSWIP automatically set the
xMII clock")
Cc: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
Reviewed-by: Florian Fainelli
Signed-off-by: David S. Miller
Signed-off-by: Greg Kroah-Hartman
!
Martin
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswip: Configure all remaining GSWIP_MII_CFG bits
drivers/net/dsa/lantiq_gswip.c | 203 -
1 file changed, 175 insertions(+), 28 deletions(-)
--
2.31.1
Hello Vladimir,
On Fri, Apr 9, 2021 at 12:46 AM Vladimir Oltean wrote:
>
> On Thu, Apr 08, 2021 at 08:38:27PM +0200, Martin Blumenstingl wrote:
> > PHY auto polling on the GSWIP hardware can be used so link changes
> > (speed, link up/down, etc.) can be detected automat
it
here to get a better overview of the GSWIP_MII_CFG register.
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa
clock")
Cc: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 185 -
1 file changed, 159 insertions(+), 26 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswi
iewed-by to the first patch (thank you!)
Best regards,
Martin
[0]
https://patchwork.kernel.org/project/netdevbpf/cover/20210406203508.476122-1-martin.blumensti...@googlemail.com/
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswip:
On Wed, Apr 7, 2021 at 9:44 PM Andrew Lunn wrote:
>
> > For my own curiosity: is there a "recommended" way where to configure
> > link up/down, speed, duplex and flow control? currently I have the
> > logic in both, .phylink_mac_config and .phylink_mac_link_up.
>
> You probably want to read the do
Hi Andrew,
On Wed, Apr 7, 2021 at 2:25 AM Andrew Lunn wrote:
[...]
> Having the MAC polling the PHY is pretty much always a bad idea.
>
> Reviewed-by: Andrew Lunn
thanks for reviewing this!
For my own curiosity: is there a "recommended" way where to configure
link up/down, speed, duplex and flo
Hello,
On Wed, Apr 7, 2021 at 6:47 PM Florian Fainelli wrote:
>
>
>
> On 4/6/2021 5:32 PM, Andrew Lunn wrote:
> >> case PHY_INTERFACE_MODE_RGMII:
> >> case PHY_INTERFACE_MODE_RGMII_ID:
> >> case PHY_INTERFACE_MODE_RGMII_RXID:
> >> case PHY_INTERFACE_MODE_RGMII_TXID:
> >>
")
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/
clock")
Cc: sta...@vger.kernel.org
Acked-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 191 -
1 file changed, 165 insertions(+), 26 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lanti
ill.
Best regards,
Martin
[0]
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=3e6fdeb28f4c331acbd27bdb0effc4befd4ef8e8
[1] https://github.com/openwrt/openwrt/pull/3085
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Don't use PHY auto polling
net: dsa: lantiq_gswi
Hello Florian, Vladimir, Hauke,
first of all: thank you very much for this very informative discussion!
On Thu, Mar 25, 2021 at 4:08 AM Florian Fainelli wrote:
[...]
> > Just to clarify, this port to queue mapping is completely optional, right?
> > You can send packets to a certain switch port t
Hi Florian,
On Thu, Mar 25, 2021 at 7:09 PM Florian Fainelli wrote:
[...]
> > It would be great to have this fix backported to Linux 5.4 and 5.10 to
> > get rid of one more blocker which prevents OpenWrt from switching to
> > this new in-tree driver.
>
> Given there is a Fixes: tag this should la
Hello,
the PMAC (Ethernet MAC) IP built into the Lantiq xRX200 SoCs has
support for multiple (TX) queues.
This MAC is connected to the SoC's built-in switch IP (called GSWIP).
Right now the lantiq_xrx200 driver only uses one TX and one RX queue.
The vendor driver (which mixes DSA/switch and MAC f
(no RX or TX traffic could be seen). Most
likely this is due to an "invalid" xMII clock being selected either by
the bootloader or hardware-defaults.
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Martin Blumenstingl
---
It would b
..3000ps in 200ps steps on older SoCs which don't
support that).
Fixes: de94fc104d58ea ("net: stmmac: dwmac-meson8b: add support for the RGMII
RX delay on G12A")
Reported-by: Martijn van Deventer
Signed-off-by: Martin Blumenstingl
---
Many thanks to Martijn for this excellen
nd 2ns. The new
SoCs have support for RGMII RX delays between 0ps and 3000ps in 200ps
steps.
Don't carry over the description for the "rx-internal-delay-ps" property
and inherit that from ethernet-controller.yaml instead.
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenst
mp;state=%2A&archive=both
[2]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=384491&state=%2A&archive=both
[3]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=406005&state=%2A&archive=both
Martin Blumenstingl (5):
dt-bindings: net: dwmac-meson: u
delay configured but the phy-mode
incicates that the RX delay is not used.
Fixes: 9308c47640d515 ("net: stmmac: dwmac-meson8b: add support for the RX
delay configuration")
Reported-by: Andrew Lunn
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
-
gic,rx-delay-ns" property (yet).
Only include minimalistic logic to fall back to the old property,
without any special validation (for example if the old and new
property are given at the same time).
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
--
future.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b
delay as well as configuring the
register accordingly on these platforms.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 61 +++
1 file changed, 48 insertions(+), 13 deletions(-)
diff
Hi Jakub,
On Mon, Jan 4, 2021 at 10:52 PM Jakub Kicinski wrote:
>
> On Sun, 3 Jan 2021 03:12:21 +0100 Martin Blumenstingl wrote:
> > Hi Andrew,
> >
> > On Sun, Jan 3, 2021 at 3:09 AM Andrew Lunn wrote:
> > >
> > > On Sun, Jan 03, 2021 at 0
Hi Andrew,
On Sun, Jan 3, 2021 at 3:09 AM Andrew Lunn wrote:
>
> On Sun, Jan 03, 2021 at 02:25:43AM +0100, Martin Blumenstingl wrote:
> > Enable GSWIP_MII_CFG_EN also for internal PHYs to make traffic flow.
> > Without this the PHY link is detected properly and ethtool statist
f the following ports: 0, 1, 5).
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Cc: sta...@vger.kernel.org
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 23 ++-
1 file changed, 6 insertions(+), 17 deletions(-
-porting them on top of
Linux 5.4.86 in OpenWrt.
Special thanks to Hauke for debugging and brainstorming this on IRC
with me!
Martin Blumenstingl (2):
net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYs
net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register access
drivers/net
")
Cc: sta...@vger.kernel.org
Suggested-by: Hauke Mehrtens
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index 09701c17f3f6..5d378c8026f0 100644
--
Hi Jakub,
On Mon, Dec 28, 2020 at 9:37 PM Jakub Kicinski wrote:
>
> On Thu, 24 Dec 2020 00:29:00 +0100 Martin Blumenstingl wrote:
> > Hello,
> >
> > with the help of Jianxin Pan (many thanks!) the meaning of the "new"
> > PRG_ETH1[19:16] register bits
nd 2ns. The new
SoCs have support for RGMII RX delays between 0ps and 3000ps in 200ps
steps.
Don't carry over the description for the "rx-internal-delay-ps" property
and inherit that from ethernet-controller.yaml instead.
Signed-off-by: Martin Blumenstingl
---
.../bindings/ne
ixes this
[0]
https://lore.kernel.org/netdev/CAFBinCATt4Hi9rigj52nMf3oygyFbnopZcsakGL=kywnsjy...@mail.gmail.com/
[1] https://patchwork.kernel.org/project/linux-amlogic/list/?series=384279
[2]
https://patchwork.kernel.org/project/linux-amlogic/list/?series=384491&state=%2A&archive=both
Martin B
gic,rx-delay-ns" property (yet).
Only include minimalistic logic to fall back to the old property,
without any special validation (for example if the old and new
property are given at the same time).
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
--
delay configured but the phy-mode
incicates that the RX delay is not used.
Fixes: 9308c47640d515 ("net: stmmac: dwmac-meson8b: add support for the RX
delay configuration")
Reported-by: Andrew Lunn
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
-
future.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b
delay as well as configuring the
register accordingly on these platforms.
Reviewed-by: Andrew Lunn
Reviewed-by: Florian Fainelli
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 61 +++
1 file changed, 48 insertions(+), 13 deletions(-)
diff
ck resource conflict with the
audio driver on G12A boards. Once the common clock framework can handle
this situation this change can be reverted again.
Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b
/ GXBB DWMAC")
Reported-by: Thomas Graichen
Signed
Hi Rob,
On Mon, Dec 7, 2020 at 8:17 PM Rob Herring wrote:
>
> On Sun, Nov 15, 2020 at 07:52:06PM +0100, Martin Blumenstingl wrote:
> > Amlogic Meson G12A, G12B and SM1 SoCs have a more advanced RGMII RX
> > delay register which allows picoseconds precision. Deprecate the o
macro and use
__ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK
macro.
Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic Meson 8b
/ GXBB DWMAC")
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
Hello Ioana,
On Mon, Nov 23, 2020 at 4:38 PM Ioana Ciornei wrote:
[...]
> Ioana Ciornei (15):
> net: phy: intel-xway: implement generic .handle_interrupt() callback
> net: phy: intel-xway: remove the use of .ack_interrupt()
> net: phy: icplus: implement generic .handle_interrupt() callback
Hi Kevin,
On Sun, Nov 15, 2020 at 7:52 PM Martin Blumenstingl
wrote:
[...]
> I have tested this on an X96 Air 4GB board (not upstream yet).
[...]
> Also I have tested this on a X96 Max board without any .dts changes
can you please add this series to your testing branch?
I am interes
Hi Florian,
On Tue, Nov 17, 2020 at 7:36 PM Florian Fainelli wrote:
>
> On 11/15/20 10:52 AM, Martin Blumenstingl wrote:
> > Amlogic Meson G12A, G12B and SM1 SoCs have a more advanced RGMII RX
> > delay register which allows picoseconds precision. Parse the new
> > &q
Amlogic Meson G12A, G12B and SM1 SoCs have a more advanced RGMII RX
delay register which allows picoseconds precision. Parse the new
"amlogic,rgmii-rx-delay-ps" property or fall back to the old
"amlogic,rx-delay-ns".
Signed-off-by: Martin Blumenstingl
---
.../ethernet/
; the RX delay is added by the PHY so
any configuration on the MAC side is ignored
- with "rmii" the RX delay is not applicable and any configuration is
ignored
Signed-off-by: Martin Blumenstingl
---
.../bindings/net/amlogic,meson-dwmac.yaml | 61 +--
1 file
delay as well as configuring the
register accordingly on these platforms.
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 61 +++
1 file changed, 48 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
he timing-adjustment clock only when really
needed. Found by Andrew - thanks!
- added testing not about X96 Max
- v1 did not go to the netdev mailing list, v2 fixes this
[0]
https://lore.kernel.org/netdev/CAFBinCATt4Hi9rigj52nMf3oygyFbnopZcsakGL=kywnsjy...@mail.gmail.com/
[1] https://patchwork
delay configured but the phy-mode
incicates that the RX delay is not used.
Fixes: 9308c47640d515 ("net: stmmac: dwmac-meson8b: add support for the RX
delay configuration")
Reported-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
future.
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index
Hi Andrew,
On Sun, Nov 15, 2020 at 4:57 PM Andrew Lunn wrote:
>
> > Add a 300ms delay after initializing all GPHYs to ensure that the GPHY
> > firmware had enough time to initialize and to appear on the MDIO bus.
> > Unfortunately there is no (known) documentation on what the minimum time
> > to
loaded to not slow down the initialization too much (
xRX200 has two GPHYs but newer SoCs have at least three GPHYs).
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
Changes since v1:
- move
loaded to not slow down the initialization too much (
xRX200 has two GPHYs but newer SoCs have at least three GPHYs).
Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 11 +++
1 fi
On Thu, Sep 24, 2020 at 3:01 AM David Miller wrote:
>
> From: Hauke Mehrtens
> Date: Tue, 22 Sep 2020 23:41:12 +0200
>
> > The TX DMA channel data is accessed by the xrx200_start_xmit() and the
> > xrx200_tx_housekeeping() function from different threads. Make sure the
> > accesses are synchroniz
Hi Andrew,
On Sat, Sep 26, 2020 at 4:45 PM Andrew Lunn wrote:
>
> > I checked this again for the vendor u-boot (where Ethernet is NOT
> > working) as well as the Android kernel which this board was shipped
> > with (where Ethernet is working)
> > - in u-boot the MAC side adds a 2ns TX delay and t
Hi Andrew,
On Sat, Sep 26, 2020 at 2:41 AM Andrew Lunn wrote:
>
> > The reference code I linked tries to detect the RGMII interface mode.
> > However, for each board we know the phy-mode as well as the RX and TX
> > delay - so I'm not trying to port the RGMII interface detection part
> > to the m
Hi Andrew,
On Sat, Sep 26, 2020 at 12:14 AM Andrew Lunn wrote:
>
> On Fri, Sep 25, 2020 at 11:47:18PM +0200, Martin Blumenstingl wrote:
> > Hello,
> >
> > Amlogic's 12nm SoC generation requires some RGMII timing calibration
> > within the Ethernet controller g
Hi Vladimir,
On Sat, Sep 26, 2020 at 12:03 AM Vladimir Oltean wrote:
[...]
> > Any recommendations/suggestions/ideas/hints are welcome!
> > Thank you and best regards,
> > Martin
> >
> >
> > [0]
> > https://github.com/khadas/u-boot/blob/4752efbb90b7d048a81760c67f8c826f14baf41c/drivers/net/design
ic to write this register will be added
later.
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 28 +++
1 file changed, 28 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/
Hello,
Amlogic's 12nm SoC generation requires some RGMII timing calibration
within the Ethernet controller glue registers.
This calibration is only needed for the RGMII modes, not for the
(internal) RMII PHY.
With "incorrect" calibration settings Ethernet speeds up to 100Mbit/s
will still work fin
ure the
> > accesses are synchronized by acquiring the netif_tx_lock() in the
> > xrx200_tx_housekeeping() function too. This lock is acquired by the
> > kernel before calling xrx200_start_xmit().
> >
> > Signed-off-by: Hauke Mehrtens
Tested-by: Martin Blumenstingl
>
RQs only if NAPI gets scheduled
for all four:
Tested-by: Martin Blumenstingl
Thank you!
Martin
rty bindings.
Fixes: 1cc2d0e021f867 ("dt-bindings: net: bluetooth: Add rtl8723bs-bluetooth")
Signed-off-by: Martin Blumenstingl
---
Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings
Simplify meson8b_init_rgmii_tx_clk() by using struct clk_parent_data to
initialize the clock parents. No functional changes intended.
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 49 +++
1 file changed, 17 insertions(+), 32 deletions
eems to be related to RGMII Ethernet.
Add a compatible string for G12A and newer so the new registers can be
used.
Signed-off-by: Martin Blumenstingl
---
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bi
eems to be related to RGMII Ethernet.
Add a new compatible string for G12A SoCs so the logic for this new
register can be implemented in the future.
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 4
1 file changed, 4 insertions(+)
diff --git a/d
first preparation step to improve Ethernet support on these SoCs.
Martin Blumenstingl (2):
dt-bindings: net: dwmac-meson: Add a compatible string for G12A
onwards
net: stmmac: dwmac-meson8b: add a compatible string for G12A SoCs
.../devicetree/bindings/net/amlogic,meson-dwmac.yaml
Lantiq / Intel DSA driver for vrx200")
Signed-off-by: Martin Blumenstingl
---
drivers/net/dsa/lantiq_gswip.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index cf6fa8fede33..521ebc072903 100644
--- a/
arned about it and existing .dtbs don't specify it.
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/ne
The PRG_ETHERNET registers on Meson8b and newer SoCs can add an RX
delay. Add a property with the known supported values so it can be
configured according to the board layout.
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
.../bindings/net/amlogic,meson-dwmac.yaml
.
Suggested-by: Jianxin Pan
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac
Use FIELD_PREP() to shift a value to the correct offset based on a
bitmask instead of open-coding the logic.
No functional changes.
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 5 +++--
1 file changed, 3 insertions(+), 2
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 23 +++
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 41f3ef6bea66
-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c9ec0cb68082..1d7526ee09dd
rm64
patches yet, but these will switch to phy-mode = "rgmii-txid" with
amlogic,rx-delay-ns = <0> (because the delay seems to be provided by
the PCB trace length).
[0] https://patchwork.kernel.org/patch/11309891/
[1] https://patchwork.kernel.org/cover/11310719/
[2] https://pa
LAY and PRG_ETH0_ADJ_SKEW
registers indicates that we can even set different RX delays. However,
I could not find out how this works exactly, so for now we only support
a 2ns RX delay using the exact same way that Odroid-C1's u-boot does.
Signed-off-by: Martin Blumenstingl
---
.../ethernet/
The PRG_ETHERNET registers can add an RX delay in RGMII mode. This
requires an internal re-timing circuit whose input clock is called
"timing adjustment clock". Document this clock input so the clock can be
enabled as needed.
Reviewed-by: Andrew Lunn
Signed-off-by: Martin Blumensting
Hello Rob,
On Fri, May 1, 2020 at 11:53 PM Martin Blumenstingl
wrote:
>
> Hi Rob,
>
> On Fri, May 1, 2020 at 11:09 PM Rob Herring wrote:
> >
> > On Wed, 29 Apr 2020 22:16:35 +0200, Martin Blumenstingl wrote:
> > > The PRG_ETHERNET registers can add an RX delay i
Hi Rob,
On Fri, May 1, 2020 at 11:09 PM Rob Herring wrote:
>
> On Wed, 29 Apr 2020 22:16:35 +0200, Martin Blumenstingl wrote:
> > The PRG_ETHERNET registers can add an RX delay in RGMII mode. This
> > requires an internal re-timing circuit whose input clock is called
> >
Hi Andrew,
On Fri, May 1, 2020 at 5:44 PM Andrew Lunn wrote:
>
> > + if (rx_dly_config & PRG_ETH0_ADJ_ENABLE) {
> > + /* The timing adjustment logic is driven by a separate clock
> > */
> > + ret = meson8b_devm_clk_prepare_enable(dwmac,
> > +
Hi Andrew,
On Wed, Apr 29, 2020 at 11:29 PM Andrew Lunn wrote:
>
> > - Khadas VIM2 seems to have the RX delay built into the PCB trace
> > length. When I enable the RX delay on the PHY or MAC I can't get any
> > data through. I expect that we will have the same situation on all
> > GXBB, GX
the PCB trace length).
[0] https://patchwork.kernel.org/patch/11309891/
[1] https://patchwork.kernel.org/cover/11310719/
Martin Blumenstingl (11):
dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property
dt-bindings: net: dwmac-meson: Document the "timing-adjustment
Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8b.dtsi | 5 +++--
arch/arm/boot/dt
arned about it and existing .dtbs don't specify it.
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/st
The timing adjustment clock will need similar logic as the RGMII clock:
It has to be enabled in the driver conditionally and when the driver is
unloaded it should be disabled again. Extract the existing code for the
RGMII clock into a new function so it can be re-used.
Signed-off-by: Martin
Move the documentation for the TX delay above the PRG_ETH0_TXDLY_MASK
definition. Future commits will add more registers also with
documentation above their register bit definitions. Move the existing
comment so it will be consistent with the upcoming changes.
Signed-off-by: Martin Blumenstingl
Use FIELD_PREP() to shift a value to the correct offset based on a
bitmask instead of open-coding the logic.
No functional changes.
Signed-off-by: Martin Blumenstingl
---
drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a
Ethernet performance on Odroid-C1 where there was a huge
amount of packet loss when transmitting data due to the incorrect TX
delay.
Signed-off-by: Martin Blumenstingl
---
arch/arm/boot/dts/meson8b-odroidc1.dts| 3 +--
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 4 +---
2 files changed
LAY and PRG_ETH0_ADJ_SKEW
registers indicates that we can even set different RX delays. However,
I could not find out how this works exactly, so for now we only support
a 2ns RX delay using the exact same way that Odroid-C1's u-boot does.
Signed-off-by: Martin Blumenstingl
---
.../ethernet/
Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).
Signed-off-by: Martin Blumenstingl
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 6 ++
.
Suggested-by: Jianxin Pan
Signed-off-by: Martin Blumenstingl
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index
The PRG_ETHERNET registers can add an RX delay in RGMII mode. This
requires an internal re-timing circuit whose input clock is called
"timing adjustment clock". Document this clock input so the clock can be
enabled as needed.
Signed-off-by: Martin Blumenstingl
---
.../devicetree/bi
The PRG_ETHERNET registers on Meson8b and newer SoCs can add an RX
delay. Add a property with the known supported values so it can be
configured according to the board layout.
Signed-off-by: Martin Blumenstingl
---
.../bindings/net/amlogic,meson-dwmac.yaml | 13 +
1 file
add a glue driver for the Amlogic Meson 8b
> / GXBB DWMAC")
> Signed-off-by: Dan Carpenter
Reviewed-by: Martin Blumenstingl
thank you for catching and fixing this!
Martin
precated properties but
the description inside the .yaml file looks good to me so:
Reviewed-by: Martin Blumenstingl
Hi Alex,
On Sat, Mar 2, 2019 at 10:30 AM 陆朱伟 wrote:
>
> Hi Martin,
> Thanks for your information.
thank you for the quick reply!
> The config is related to eFuse in chips. I'm sorry that the details can't be
> open.
> Only some special configurations are related to the host platforms, such as
Hi Vasily, Hi Alex,
On 22/02/2019 11:21, Vasily Khoruzhick wrote:
> I agree with Rob that we should probably use firmware-name here instead.
Have you considered skipping this property for v1 of this series?
We can still add that property (as optional one) later on if we really
see the need for it.
Hi Anand,
On Tue, Feb 26, 2019 at 11:26 AM Anand Moon wrote:
>
> Hi Martin,
>
> On Mon, 25 Feb 2019 at 17:49, Anand Moon wrote:
> >
> > hi Martin,
> >
> > +Bartosz Golaszewski
> >
> > On Mon, 25 Feb 2019 at 02:25, Martin Blumenstingl
> > w
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