On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
ethernet QOS IP core. The binding that it uses is slightly different
from existing ones because of the integration (clocks, resets, ...).
dev_err(>dev, "failed to remove subdriver: %d\n", err);
+
+ stmmac_remove_config_dt(pdev, priv->plat);
+
+ return err;
}
static const struct of_device_id dwc_eth_dwmac_match[] = {
- { .compatible = "snps,dwc-qos-ethernet-4.10", },
+ { .compatible = "snps,dwc-qos-ethernet-4.10", .data = _qos_data },
{ }
};
MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
Program the receive queue size based on the RX FIFO size and enable
hardware flow control for large FIFOs.
Signed-off-by: Thierry Reding
---
drivers/net/ethernet/stmicro/stmmac/dwmac4.h
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
clk_prepare_enable() and clk_disable_unprepare() for this clock aren't
properly balanced, which can trigger a WARN_ON() in the common clock
framework.
Signed-off-by: Thierry Reding
---
On 23.02.2017 19:24, Thierry Reding wrote:
From: Thierry Reding
When DMA mapping an SKB fragment, the mapping must be checked for
errors, otherwise the DMA debug code will complain upon unmap.
Signed-off-by: Thierry Reding
---
fosz = priv->dma_cap.rx_fifo_size;
+
if (priv->plat->force_thresh_dma_mode)
priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com>