w a the struct dpaa_napi_portal * should be
derived from the struct qman_portal *, so revert the patch for now.
Signed-off-by: Sascha Hauer
---
This merely puts the finger in the wound, I don't know how to properly fix
this issue. If you have a better idea what should be done instead please
let me know.
On Thu, Aug 27, 2020 at 10:48:48AM +0200, Heiner Kallweit wrote:
> On 27.08.2020 09:06, Sascha Hauer wrote:
> > After device_register has been called the device structure may not be
> > freed anymore, put_device() has to be called instead. This gets violated
> > when device
then directly frees the mdio bus structure.
Set bus->state to MDIOBUS_UNREGISTERED right before calling
device_register(). With this mdiobus_free() calls put_device() instead
as it ought to be.
Signed-off-by: Sascha Hauer
---
Changes since v1:
- set bus->state before calling device_re
On Wed, Aug 26, 2020 at 06:26:36PM +0200, Heiner Kallweit wrote:
> On 26.08.2020 11:51, Sascha Hauer wrote:
> > __mdiobus_register() can fail between calling device_register() and
> > setting bus->state to MDIOBUS_REGISTERED. When this happens the caller
> > will call m
eed dropping the reference count using put_device(). To
accomplish this set bus->state to MDIOBUS_UNREGISTERED after having
registered the device. With this mdiobus_free() correctly calls
put_device() instead of freeing the mdio bus structure directly.
Signed-off-by: Sascha Hauer
---
drivers/n
Hi Andrew,
On Tue, Aug 25, 2020 at 03:14:00PM +0200, Andrew Lunn wrote:
> On Tue, Aug 25, 2020 at 11:09:33AM +0200, Sascha Hauer wrote:
> > Hi All,
> >
> > I am using the ethernet phy binding here that looks like:
> >
> > ethphy1: ethernet-phy@1 {
> >
Hi All,
I am using the ethernet phy binding here that looks like:
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
eee-broken-1000t;
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
};
It seems the "reset-gpios" is inherently broken in Linu
On Fri, Aug 14, 2020 at 08:27:56AM -0700, Stephen Hemminger wrote:
> On Fri, 14 Aug 2020 10:46:26 +0200
> Sascha Hauer wrote:
>
> > ip maddress add|del takes a MAC address as argument, so insist on
> > getting a length of ETH_ALEN bytes. This makes sure the passed argument
in the error path as this has been
modified by ll_addr_a2n() and doesn't contain the full string anymore,
which can lead to misleading error messages.
Also while at it, replace the hardcoded buffer size with the actual
buffer size using sizeof().
Signed-off-by: Sascha Hauer
---
Changes sin
in the error path as this has been
modified by ll_addr_a2n() and doesn't contain the full string anymore,
which can lead to misleading error messages.
Signed-off-by: Sascha Hauer
---
ip/ipmaddr.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/ip/ipmaddr.c
SolidRun Clearfog:
WARNING: CPU: 0 PID: 268 at drivers/net/ethernet/marvell/mvneta.c:3512
mvneta_start_dev+0x220/0x23c
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
valid interface modes early so that
later in the driver we do not have to care for unexpected interface
modes.
Add back the test to let the driver bail out early on unhandled
interface modes.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 22 +++---
1 file
On Tue, Jun 23, 2020 at 12:53:40AM +0100, Russell King - ARM Linux admin wrote:
> On Tue, Jun 16, 2020 at 10:31:39AM +0200, Sascha Hauer wrote:
> > The MVNETA_SERDES_CFG register is only available on older SoCs like the
> > Armada XP. On newer SoCs like the Armada 38x the fiel
configured.
With this we no longer write to the MVNETA_SERDES_CFG on SoCs where it
doesn't exist.
Suggested-by: Russell King
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 80 +++
1 file changed, 44 insertions(+), 36 deletions(-)
diff --
writing the correct magic value into
the MVNETA_SERDES_CFG register.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 9933eb4577d43
Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > > > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > > > called DRSGMII. Depending on the Port MAC Control Register0 PortType
> > > > setting this seems to be either an overclocke
On Fri, Jun 12, 2020 at 12:30:31PM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 12:22:13PM +0100, Russell King - ARM Linux admin
> wrote:
> > On Fri, Jun 12, 2020 at 11:42:08AM +0100, Russell King - ARM Linux admin
> > wrote:
> > > With the obvious mistakes fixed (extran
On Fri, Jun 12, 2020 at 09:47:10AM +0100, Russell King - ARM Linux admin wrote:
> On Fri, Jun 12, 2020 at 10:38:47AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Control Reg
differentiate the different
possibilities.
Fixes: da58a931f248f ("net: mvneta: Add support for 2500Mbps SGMII")
Signed-off-by: Sascha Hauer
---
Changes since v1:
- Add Fixes: tag
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git
Hi Andrew,
+Cc Maxime Chevallier
On Tue, Jun 09, 2020 at 03:28:48PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 03:11:52PM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5Gbps SGMII mode
> > called DRSGMII. Depending on the Port MAC Co
Hi Andrew,
On Tue, Jun 09, 2020 at 03:12:16PM +0200, Andrew Lunn wrote:
> On Tue, Jun 09, 2020 at 02:55:35PM +0200, Sascha Hauer wrote:
> > On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> > > On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> >
differentiate the different
possibilities.
Signed-off-by: Sascha Hauer
---
drivers/net/ethernet/marvell/mvneta.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell/mvneta.c
index 51889770958d8..3b13048931412
On Mon, Jun 08, 2020 at 04:57:37PM +0200, Andrew Lunn wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a corresponding phy-mode
On Mon, Jun 08, 2020 at 05:08:01PM +0100, Russell King - ARM Linux admin wrote:
> On Mon, Jun 08, 2020 at 09:47:16AM +0200, Sascha Hauer wrote:
> > The Marvell MVNETA Ethernet controller supports a 2.5 Gbps SGMII mode
> > called DRSGMII.
> >
> > This patch adds a co
to a FPGA.
Signed-off-by: Sascha Hauer
---
.../devicetree/bindings/net/ethernet-controller.yaml | 1 +
drivers/net/ethernet/marvell/mvneta.c | 7 ++-
include/linux/phy.h| 3 +++
3 files changed, 10 insertions(+), 1 deletion(-)
On Mon, May 25, 2020 at 03:09:26PM +0800, fugang.d...@nxp.com wrote:
> From: Fugang Duan
>
> The commit da722186f654 (net: fec: set GPR bit on suspend by DT
> configuration) set the GPR reigster offset and bit in driver for
> wake on lan feature.
>
> But it introduces two issues here:
> - one SO
On Sun, May 10, 2020 at 07:02:13PM +0800, zhoubo...@foxmail.com wrote:
> From: To-run-away
>
> Increase the use of dm9000 to initialize the SROM_BANK clock in the SOC,
> otherwise the chip will not work.
The dm9000 doesn't have anything called SROM in it. You have to
describe the clock input pin
Hi Madalin,
On Thu, Apr 23, 2020 at 12:59:16PM +, Madalin Bucur wrote:
> > -Original Message-
> > From: Sascha Hauer
> > Sent: Thursday, April 23, 2020 1:22 PM
> > To: linux-arm-ker...@lists.infradead.org
> > Cc: Madalin Bucur ; Shawn Guo
> > ; Le
Hi Florian,
On Wed, Sep 18, 2019 at 10:41:58AM -0700, Florian Fainelli wrote:
> On 9/18/19 7:36 AM, Vladimir Oltean wrote:
> > Hi Sascha,
> >
> > On Wed, 18 Sep 2019 at 17:03, Sascha Hauer wrote:
> >>
> >> Hi All,
> >>
> >> We have a cus
On Thu, Sep 19, 2019 at 11:18:24AM +0300, Vladimir Oltean wrote:
> On Thu, 19 Sep 2019 at 11:00, Sascha Hauer wrote:
> >
> > Hi Vladimir,
> >
> > On Wed, Sep 18, 2019 at 05:36:08PM +0300, Vladimir Oltean wrote:
> > > Hi Sascha,
> > >
> >
Hi Vladimir,
On Wed, Sep 18, 2019 at 05:36:08PM +0300, Vladimir Oltean wrote:
> Hi Sascha,
>
> On Wed, 18 Sep 2019 at 17:03, Sascha Hauer wrote:
> >
> > Hi All,
> >
> > We have a customer using a Marvell 88e6240 switch with Ethercat on one port
> > and
Hi All,
We have a customer using a Marvell 88e6240 switch with Ethercat on one port and
regular network traffic on another port. The customer wants to configure two
things
on the switch: First Ethercat traffic shall be priorized over other network
traffic
(effectively prioritizing traffic based
On Mon, Jun 20, 2016 at 07:14:06PM +0200, Oliver Graute wrote:
> On 20/06/16, Andrew Lunn wrote:
> > > &fec1 {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_enet1>;
> > > phy-mode = "rmii";
> > > micrel,rmii-reference-clock-select-25-mhz;
> > > clocks,rmii-ref;
> >
> > You
On Mon, Jun 20, 2016 at 03:56:10PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 6/20/2016 3:08 PM, Oliver Graute wrote:
>
> >thx you both for confirming that. Can you tell me also if the clock
> >statement s fine in my dts?
> >
> >&fec1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&
On Sun, Jun 19, 2016 at 09:29:41PM +0200, Oliver Graute wrote:
> On 17/06/16, Sergei Shtylyov wrote:
> > On 06/17/2016 04:04 PM, Oliver Graute wrote:
> >
> > >I try to enable a Micrel KSZ8031 in my imx6ul board device tree. But i'am
> > >struggeling with the setting for KSZPHY_RMII_REF_CLK_SEL BIT
The phy has not been initialized, disconnecting it in the error
path results in a NULL pointer exception. Drop the phy_disconnect
from the error path.
Signed-off-by: Sascha Hauer
---
net/dsa/slave.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index
The Marvell 88E6240 has been tested successfully without further
changes. Add entry to the table of supported devices.
Signed-off-by: Sascha Hauer
---
drivers/net/dsa/mv88e6352.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/dsa/mv88e6352.c b/drivers/net/dsa/mv88e6352.c
index
On Fri, Dec 11, 2015 at 10:40:22AM +0100, Gregory CLEMENT wrote:
> Hi Sascha,
>
> On ven., déc. 11 2015, Sascha Hauer wrote:
>
> > On Thu, Dec 10, 2015 at 04:08:08PM +0100, Gregory CLEMENT wrote:
> >> Hi Sascha,
> >>
> >> On jeu., déc. 10 2015,
On Thu, Dec 10, 2015 at 04:08:08PM +0100, Gregory CLEMENT wrote:
> Hi Sascha,
>
> On jeu., déc. 10 2015, Sascha Hauer wrote:
>
> > Hi Gregory,
> >
> > On Wed, Dec 09, 2015 at 06:49:43PM +0100, Gregory CLEMENT wrote:
> >> With device tree it is no
Hi Gregory,
On Wed, Dec 09, 2015 at 06:49:43PM +0100, Gregory CLEMENT wrote:
> With device tree it is no more possible to reset the PHY at board
> level. Furthermore, doing in the driver allow to power down the PHY when
> the network interface is no more used.
>
> The patch introduces a new optio
Hi Domen,
On Sun, Sep 02, 2007 at 09:41:43AM +0200, Domen Puncer wrote:
+ */
> +static void fec_start(struct net_device *dev)
> +{
> + struct fec_priv *priv = netdev_priv(dev);
> + struct mpc52xx_fec __iomem *fec = priv->fec;
> + u32 rcntrl;
> + u32 tcntrl;
> + u32 tmp;
> +
>
Hi,
I made a quick shot to port the at91 network driver to the phy
abstraction layer. While doing so I stumbled upon the
(struct mii_bus)->id field. Currently the network driver registering the
bus has to set this field. au1000_eth.c for example uses 0 or 1. mii-fec.c
uses the id field of the corr
patch fix this problem.
>
>
> Signed-off-by: Dirk Opfer <[EMAIL PROTECTED]>
I thought this was fixed long ago, it must have been lost somewhere.
Anyway:
Acked-by: Sascha Hauer <[EMAIL PROTECTED]>
--
Dipl.-Ing. Sascha Hauer | http://www.pengutronix.de
Pengutronix - Li
This patch also moves the version printk() to the init call, so that
> you only get it once for multiple devices, and to show it is loaded
> if there are no defined dm9000s
>
> Signed-off-by: Ben Dooks <[EMAIL PROTECTED]>
>
acked-by: Sascha Hauer <[EMAIL PROTECTED]>
-
To
) and not spin_xxx(&lock)
>
> 3) move the locking around the phy reg for read/write to only
>keep the lock when actually reading or writing to the phy.
>
> Signed-off-by: Ben Dooks <[EMAIL PROTECTED]>
>
Good to see someone else has better eyes than me ;)
acked-by:
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