Rob Herring wrote:
>+ interrupt-parent = <&emac0>;
>+ #interrupt-cells = <1>;
>+ interrupts = <0 1>;
>+ interrupt-map-mask = <0x>;
>+ interrupt-map = <0 &intc 0 76 0
>+1 &intc 0 80 0>;
Why? This looks unnecessa
Shanker Donthineni wrote:
/* Set dma_mask and coherent_dma_mask to 64-bits,
* if xHC supports 64-bit addressing */
if (HCC_64BIT_ADDR(xhci->hcc_params) &&
!dma_set_mask(dev, DMA_BIT_MASK(64))) {
xhci_dbg(xhci, "Enabling 64-bit
Timur,
I think, the device driver is responsible for setting the right DMA_MASK
based on the underlying hardware capability if your driver wants to
support 64bit DMA.
Example code in drivers/usb/host/xhci.c:
/* Set dma_mask and coherent_dma_mask to 64-bits,
* if xHC supports
Rob Herring wrote:
>+ dma-ranges = <0 0 0x>;
I believe dma-ranges is supposed to be in the bus (parent) node.
Maybe I'm just going to be perpetually confused by dma-ranges, but how
can I specify that the emac has a different DMA range from another SOC
device, if dma-ranges
On Tue, Jun 14, 2016 at 05:22:35PM -0500, Timur Tabi wrote:
> Add supports for ethernet controller HW on Qualcomm Technologies, Inc. SoC.
> This driver supports the following features:
> 1) Checksum offload.
> 2) Interrupt coalescing support.
> 3) SGMII phy.
> 4) phylib interface for external phy
>
David Miller wrote:
Please always order local variable declarations from longest to shortest
line.
Audit your entire driver for this issue, thanks.
I will fix this in v6.
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
Cod
From: Timur Tabi
Date: Tue, 14 Jun 2016 17:22:35 -0500
> +/* Free all descriptors of given receive queue */
> +static void emac_rx_q_free_descs(struct emac_adapter *adpt)
> +{
> + struct emac_rx_queue *rx_q = &adpt->rx_q;
> + struct device *dev = adpt->netdev->dev.parent;
> + size_t s
Add supports for ethernet controller HW on Qualcomm Technologies, Inc. SoC.
This driver supports the following features:
1) Checksum offload.
2) Interrupt coalescing support.
3) SGMII phy.
4) phylib interface for external phy
Based on original work by
Niranjana Vishwanathapura
Gil
