On Wed, 2017-07-12 at 16:50 +0200, Andrew Lunn wrote:
> > +static int mtk_clk_enable(struct mtk_eth *eth)
> > +{
> > + int clk, ret;
> > +
> > + for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
> > + if (eth->clks[clk]) {
> > + ret = clk_prepare_enable(eth->clks[clk]);
>
> +static int mtk_clk_enable(struct mtk_eth *eth)
> +{
> + int clk, ret;
> +
> + for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
> + if (eth->clks[clk]) {
> + ret = clk_prepare_enable(eth->clks[clk]);
> + if (ret)
> +
On 07/11/2017 08:37 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> This patch is the preparation patch in order to adapt into various
> hardware through adding platform data which holds specific characteristics
> among MediaTek SoCs and introducing the unified
From: Sean Wang
This patch is the preparation patch in order to adapt into various
hardware through adding platform data which holds specific characteristics
among MediaTek SoCs and introducing the unified clock handler for those
distinct clock requirements depending on