On Tuesday, July 19, 2016 10:40:16 AM CEST Jamie Lentin wrote:
> On Mon, 18 Jul 2016, Arnd Bergmann wrote:
>
> > On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
> >>
> >> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> >>
> >>> I would assume that the PCIe port should
On Sun, 17 Jul 2016, Rob Herring wrote:
On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
This is a router based on the mv88f5181 chipset.
http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t
Signed-off-by: Jamie Lentin
---
.../bindings
On Mon, 18 Jul 2016, Arnd Bergmann wrote:
On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires
On Monday, July 18, 2016 11:44:24 AM CEST Thomas Petazzoni wrote:
>
> On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
>
> > I would assume that the PCIe port should work out of the box with the driver
>
> Unfortunately, no. The PCIe on Orion5x requires a workaround for
> reading/writing
Hello,
On Sun, 17 Jul 2016 22:41:35 +0200, Arnd Bergmann wrote:
> I would assume that the PCIe port should work out of the box with the driver
Unfortunately, no. The PCIe on Orion5x requires a workaround for
reading/writing the PCI configuration space. Instead of doing MMIO
accesses to PCIE_CONF
On Sat, Jul 16, 2016 at 03:29:04PM +0100, Jamie Lentin wrote:
> This is a router based on the mv88f5181 chipset.
>
> http://www.netgear.com/support/product/WNR854T.aspx
> http://wiki.openwrt.org/toh/netgear/wnr854t
>
> Signed-off-by: Jamie Lentin
> ---
> .../bindings/arm/marvell/marvell,orion5x
On Sunday, July 17, 2016 10:39:01 AM CEST Jamie Lentin wrote:
> On Sat, 16 Jul 2016, Arnd Bergmann wrote:
> > The other patches all appear good to me, but I find this one suspicious.
> >
> > Why are you not using the device tree for probing PCI? Is there anything
> > missing in drivers/pci/host/pc
On Sat, 16 Jul 2016, Arnd Bergmann wrote:
On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
+
+#define WNR854T_PCI_SLOT0_OFFS 7
+#define WNR854T_PCI_SLOT0_IRQ_PIN 4
+
+static void __init wnr854t_pci_preinit(void)
+{
+ int pin;
+
+ /*
+* Configure PCI GPIO I
On Saturday, July 16, 2016 3:29:04 PM CEST Jamie Lentin wrote:
> +
> +#define WNR854T_PCI_SLOT0_OFFS 7
> +#define WNR854T_PCI_SLOT0_IRQ_PIN4
> +
> +static void __init wnr854t_pci_preinit(void)
> +{
> + int pin;
> +
> + /*
> + * Configure PCI GPIO IRQ pins
> + */
> +
> + pmx_reset_switch: pmx-reset-switch {
> + marvell,pins = "mpp1";
> + marvell,function = "gpio";
> + };
Ah! I think i interpreted that wrong. This does not reset the Ethernet
switch. It is actually a switch on the front to reset the whole box?
How about calling i
> + chosen {
> + bootargs = "console=ttyS0,115200n8 earlyprintk";
> + linux,stdout-path = &uart0;
> + };
You can put the board rate etc in the stdout-patch. Something like:
stdout-path = "serial0:115200n8";
> + gpio-leds {
> + compa
This is a router based on the mv88f5181 chipset.
http://www.netgear.com/support/product/WNR854T.aspx
http://wiki.openwrt.org/toh/netgear/wnr854t
Signed-off-by: Jamie Lentin
---
.../bindings/arm/marvell/marvell,orion5x.txt | 1 +
arch/arm/boot/dts/Makefile | 1 +
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