Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

2016-11-29 Thread David Miller
From: Zumeng Chen Date: Mon, 28 Nov 2016 21:55:00 +0800 > When a hardware issue happened as described by inline comments, the register > write pattern looks like the following: > > > + wmb(); > > > There might be a memory barrier between these two write operations, so add wmb > to ensure an f

Re: [PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

2016-11-28 Thread Nicolas Ferre
Le 28/11/2016 à 14:55, Zumeng Chen a écrit : > When a hardware issue happened as described by inline comments, the register > write pattern looks like the following: > > > + wmb(); > > > There might be a memory barrier between these two write operations, so add wmb > to ensure an flip from 0 to

[PATCH v2 1/1] net: macb: ensure ordering write to re-enable RX smoothly

2016-11-28 Thread Zumeng Chen
When a hardware issue happened as described by inline comments, the register write pattern looks like the following: + wmb(); There might be a memory barrier between these two write operations, so add wmb to ensure an flip from 0 to 1 for NCR. Signed-off-by: Zumeng Chen --- V2 changes: Add