| From: Raj, Ashok
| Sent: Wednesday, August 9, 2017 11:00 AM
|
| On Wed, Aug 09, 2017 at 04:46:07PM +, Casey Leedom wrote:
| > | From: Raj, Ashok
| > | Sent: Wednesday, August 9, 2017 8:58 AM
| > | ...
| > | As Casey pointed out in an earlier thread, we choose the heavy hammer
| > | approach
On Wed, Aug 09, 2017 at 04:46:07PM +, Casey Leedom wrote:
> | From: Raj, Ashok
> | Sent: Wednesday, August 9, 2017 8:58 AM
> | ...
> | As Casey pointed out in an earlier thread, we choose the heavy hammer
> | approach because there are some that can lead to data-corruption as opposed
> | to pe
| From: Raj, Ashok
| Sent: Wednesday, August 9, 2017 8:58 AM
| ...
| As Casey pointed out in an earlier thread, we choose the heavy hammer
| approach because there are some that can lead to data-corruption as opposed
| to perf degradation.
Careful. As far as I'm aware, there is no Data Corruptio
| From: Ding Tianhong
| Sent: Wednesday, August 9, 2017 5:17 AM
|
| On 2017/8/9 11:02, Bjorn Helgaas wrote:
| >
| > On Wed, Aug 09, 2017 at 01:40:01AM +, Casey Leedom wrote:
| > >
| >> | From: Bjorn Helgaas
| >> | Sent: Tuesday, August 8, 2017 4:22 PM
| >> | ...
| >> | It should also include
Hi Bjorn
On Tue, Aug 08, 2017 at 06:22:00PM -0500, Bjorn Helgaas wrote:
> On Sat, Aug 05, 2017 at 03:15:10PM +0800, Ding Tianhong wrote:
> > From: Casey Leedom
> >
> > Root complexes don't obey PCIe 3.0 ordering rules, hence could lead to
> > data-corruption.
>
> This needs to include a link to
On 2017/8/9 11:02, Bjorn Helgaas wrote:
> On Wed, Aug 09, 2017 at 01:40:01AM +, Casey Leedom wrote:
>> | From: Bjorn Helgaas
>> | Sent: Tuesday, August 8, 2017 4:22 PM
>> |
>> | This needs to include a link to the Intel spec
>> |
>> (https://software.intel.com/sites/default/files/managed/9
On Wed, Aug 09, 2017 at 01:40:01AM +, Casey Leedom wrote:
> | From: Bjorn Helgaas
> | Sent: Tuesday, August 8, 2017 4:22 PM
> |
> | This needs to include a link to the Intel spec
> |
> (https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pd
| From: Bjorn Helgaas
| Sent: Tuesday, August 8, 2017 4:22 PM
|
| This needs to include a link to the Intel spec
|
(https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf,
| sec 3.9.1).
In the commit message or as a comment? Regardless, I
On Sat, Aug 05, 2017 at 03:15:10PM +0800, Ding Tianhong wrote:
> From: Casey Leedom
>
> The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that
> Relaxed Ordering (RO) attribute should not be used for Transaction Layer
> Packets (TLP) targetted towards these affected root com
From: Casey Leedom
The patch adds a new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING to indicate that
Relaxed Ordering (RO) attribute should not be used for Transaction Layer
Packets (TLP) targetted towards these affected root complexes. Current list
of affected parts include some Intel Xeon processors
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