On Tue, Jan 16, 2018 at 12:20 PM, Martin Blumenstingl
wrote:
> On Sun, Jan 14, 2018 at 10:48 PM, Martin Blumenstingl
> wrote:
>> Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
>> RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
>> - bit 4 is a mux to choos
On Sun, Jan 14, 2018 at 10:48 PM, Martin Blumenstingl
wrote:
> Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
> RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
> - bit 4 is a mux to choose between two parent clocks. according to the
> public S805 datashe
On Mon, 2018-01-15 at 13:08 +0100, Martin Blumenstingl wrote:
> can you share your thoughts how to do this?
> I can devm_kzalloc the memory for struct clk_mux, clk_divider and
> clk_fixed_factor in the function which registers these clocks. but I
> cannot declare them on the stack, because the clk-
Hi Jerome,
On Mon, Jan 15, 2018 at 12:49 PM, Jerome Brunet wrote:
> On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote:
>> Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
>> RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
>> - bit 4 is a mux to c
On Sun, 2018-01-14 at 22:48 +0100, Martin Blumenstingl wrote:
> Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
> RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
> - bit 4 is a mux to choose between two parent clocks. according to the
> public S805 datashe
Tests (using an oscilloscope and an Odroid-C1 board with a RTL8211F
RGMII PHY) have shown that the PRG_ETH0 register behaves as follows:
- bit 4 is a mux to choose between two parent clocks. according to the
public S805 datasheet the only supported parent clock is MPLL2 (this
was not verified u