Re: [RFC PATCH 0/6] Introduce combined AES-GCM assembly for POWER9+

2021-05-20 Thread Maamoun TK
On Thu, May 20, 2021 at 10:06 PM Niels Möller wrote: > "Christopher M. Riedl" writes: > > > So in total, if we assume an ideal (but impossible) zero-cost version > > for memxor, memxor3, and gcm_fill and avoid permutes via ISA 3.0 vector > > load/stores we can only account for 11.82

Re: [Aarch64] Optimize SHA1 Compress

2021-05-20 Thread Maamoun TK
I've mentioned it in the README file. --- arm64/README | 7 +++ arm64/crypto/sha1-compress.asm | 6 -- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arm64/README b/arm64/README index d2745d57..206bb773 100644 --- a/arm64/README +++ b/arm64/README @@

Re: [RFC PATCH 0/6] Introduce combined AES-GCM assembly for POWER9+

2021-05-20 Thread Niels Möller
"Christopher M. Riedl" writes: > So in total, if we assume an ideal (but impossible) zero-cost version > for memxor, memxor3, and gcm_fill and avoid permutes via ISA 3.0 vector > load/stores we can only account for 11.82 cycles/block; leaving 4.97 > cycles/block as an additional benefit of the

Re: [Aarch64] Optimize SHA1 Compress

2021-05-20 Thread Maamoun TK
On Thu, May 20, 2021 at 9:16 PM Niels Möller wrote: > Maamoun TK writes: > > > I've written the patch from scratch while keeping in mind how to use the > > SHA-1 instructions of Arm64 crypto extension from sha1-arm.c in Jeffrey's > > repository. > > If that is the case, avoid phrases like

Re: [Aarch64] Optimize SHA1 Compress

2021-05-20 Thread Niels Möller
Maamoun TK writes: > I've written the patch from scratch while keeping in mind how to use the > SHA-1 instructions of Arm64 crypto extension from sha1-arm.c in Jeffrey's > repository. If that is the case, avoid phrases like "based on" which are easily misread as implying it's a derived work in