Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-11 Thread Peter Wu
On Fri, Sep 07, 2018 at 05:26:47PM -0500, Bjorn Helgaas wrote: > [+cc LKML, Dave, Luming] > > On Fri, Sep 07, 2018 at 05:05:15PM +0200, Peter Wu wrote: > > On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: > > <..> > > > Thomas Martitz reports that this workaround also solves an issue

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-11 Thread Bjorn Helgaas
[+cc LKML, Dave, Luming] On Fri, Sep 07, 2018 at 05:05:15PM +0200, Peter Wu wrote: > On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: > <..> > > Thomas Martitz reports that this workaround also solves an issue where > > the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unrespons

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-11 Thread Sinan Kaya
On 9/6/2018 10:36 PM, Daniel Drake wrote: + if (pci_dev->class == PCI_CLASS_BRIDGE_PCI << 8) + pci_setup_bridge_mmio_pref(pci_dev); This should probably some kind of a quirk rather than default for the listed card as it sounds like you are dealing with broken hardware. _

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-11 Thread Rafael J. Wysocki
On Tuesday, September 11, 2018 5:35:13 AM CEST Daniel Drake wrote: > I have created https://bugzilla.kernel.org/show_bug.cgi?id=201069 to > archive the research done so far. > > On Fri, Sep 7, 2018 at 11:05 PM, Peter Wu wrote: > > Windows 10 unconditionally rewrites these registers (BAR, I/O Base

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-10 Thread Daniel Drake
I have created https://bugzilla.kernel.org/show_bug.cgi?id=201069 to archive the research done so far. On Fri, Sep 7, 2018 at 11:05 PM, Peter Wu wrote: > Windows 10 unconditionally rewrites these registers (BAR, I/O Base + > Limit, Memory Base + Limit, etc. from top to bottom), see annotations: >

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-10 Thread Thomas Martitz
Hello Daniel, Am 07.09.18 um 07:36 schrieb Daniel Drake: On 38+ Intel-based Asus products, the nvidia GPU becomes unusable after S3 suspend/resume. The affected products include multiple generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs many errors such as: fifo: fault

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-08 Thread Thomas Martitz
Am 07.09.18 um 17:05 schrieb Peter Wu: On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: <..> Thomas Martitz reports that this workaround also solves an issue where the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive after S3 suspend/resume. Where was this claimed?

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-07 Thread Bjorn Helgaas
[+cc LKML] On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: > On 38+ Intel-based Asus products, the nvidia GPU becomes unusable > after S3 suspend/resume. The affected products include multiple > generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs > many errors such

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-07 Thread Peter Wu
On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: <..> > Thomas Martitz reports that this workaround also solves an issue where > the AMD Radeon Polaris 10 GPU on the HP Zbook 14u G5 is unresponsive > after S3 suspend/resume. Where was this claimed? It is not stated in the linked bug:

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-07 Thread Daniel Drake
On Fri, Sep 7, 2018 at 2:40 PM, Sinan Kaya wrote: > On 9/6/2018 10:36 PM, Daniel Drake wrote: >> >> + if (pci_dev->class == PCI_CLASS_BRIDGE_PCI << 8) >> + pci_setup_bridge_mmio_pref(pci_dev); > > > This should probably some kind of a quirk rather than default > for the listed

Re: [Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-06 Thread Lukas Wunner
On Fri, Sep 07, 2018 at 01:36:14PM +0800, Daniel Drake wrote: > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -934,6 +934,7 @@ struct pci_dev *pci_scan_single_device(struct pci_bus > *bus, int devfn); > void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); > unsigned int pc

[Nouveau] [PATCH] PCI: Reprogram bridge prefetch registers on resume

2018-09-06 Thread Daniel Drake
On 38+ Intel-based Asus products, the nvidia GPU becomes unusable after S3 suspend/resume. The affected products include multiple generations of nvidia GPUs and Intel SoCs. After resume, nouveau logs many errors such as: fifo: fault 00 [READ] at 00555000 engine 00 [GR] client 04 [HUB/F