tFAW, tCKE, tXPDLL, derived from datasheets. Merge skeggsb's:
"bios/rammap: make unknown timing 1.0 fields match 2.0's naming"
Signed-off-by: Roy Spliet <nouv...@spliet.org>
---
.../drm/nouveau/include/nvkm/subdev/bios/ramcfg.h | 12 +++----
drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c | 42 +++++++++++-----------
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 14 ++++----
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 6 ++--
4 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
index dca6c06..d8a7c04 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h
@@ -127,17 +127,17 @@ struct nvbios_ramcfg {
unsigned timing_10_RCDRD:8;
unsigned timing_10_RCDWR:8;
unsigned timing_10_RRD:8;
- unsigned timing_10_13:8;
+ unsigned timing_10_XPDLL:8;
unsigned timing_10_ODT:3;
/* empty: 15 */
- unsigned timing_10_16:8;
+ unsigned timing_10_10:8;
/* empty: 17 */
- unsigned timing_10_18:8;
+ unsigned timing_10_12:8;
unsigned timing_10_CWL:8;
- unsigned timing_10_20:8;
- unsigned timing_10_21:8;
+ unsigned timing_10_FAW:8;
+ unsigned timing_10_CKE:8;
/* empty: 22, 23 */
- unsigned timing_10_24:8;
+ unsigned timing_10_18:8;
};
struct {
unsigned timing_20_2e_03:2;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
index 7e83c39..c36be13 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.c
@@ -100,34 +100,34 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
p->timing_10_RCDRD = nvbios_rd08(bios, data + 0x0a);
p->timing_10_RCDWR = nvbios_rd08(bios, data + 0x0b);
p->timing_10_RRD = nvbios_rd08(bios, data + 0x0c);
- p->timing_10_13 = nvbios_rd08(bios, data + 0x0d);
+ p->timing_10_XPDLL = nvbios_rd08(bios, data + 0x0d);
p->timing_10_ODT = nvbios_rd08(bios, data + 0x0e) & 0x07;
if (p->ramcfg_ver >= 0x10)
p->ramcfg_RON = nvbios_rd08(bios, data + 0x0e) & 0x07;
- p->timing_10_24 = 0xff;
- p->timing_10_21 = 0;
- p->timing_10_20 = 0;
+ p->timing_10_18 = 0xff;
+ p->timing_10_CKE = 0;
+ p->timing_10_FAW = 0;
p->timing_10_CWL = 0;
- p->timing_10_18 = 0;
- p->timing_10_16 = 0;
+ p->timing_10_12 = 0;
+ p->timing_10_10 = 0;
- switch (min_t(u8, *hdr, 25)) {
- case 25:
- p->timing_10_24 = nvbios_rd08(bios, data + 0x18);
- case 24:
- case 23:
- case 22:
- p->timing_10_21 = nvbios_rd08(bios, data + 0x15);
- case 21:
- p->timing_10_20 = nvbios_rd08(bios, data + 0x14);
- case 20:
+ switch (min_t(u8, *hdr, 0x19)) {
+ case 0x19:
+ p->timing_10_18 = nvbios_rd08(bios, data + 0x18);
+ case 0x18:
+ case 0x17:
+ case 0x16:
+ p->timing_10_CKE = nvbios_rd08(bios, data + 0x15);
+ case 0x15:
+ p->timing_10_FAW = nvbios_rd08(bios, data + 0x14);
+ case 0x14:
p->timing_10_CWL = nvbios_rd08(bios, data + 0x13);
- case 19:
- p->timing_10_18 = nvbios_rd08(bios, data + 0x12);
- case 18:
- case 17:
- p->timing_10_16 = nvbios_rd08(bios, data + 0x10);
+ case 0x13:
+ p->timing_10_12 = nvbios_rd08(bios, data + 0x12);
+ case 0x12:
+ case 0x11:
+ p->timing_10_10 = nvbios_rd08(bios, data + 0x10);
}
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
index f106643..dd80de1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
@@ -373,7 +373,7 @@ gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
- max_t(u8,T(18), 1) << 16 |
+ max_t(u8,T(12), 1) << 16 |
(T(WTR) + 1 + T(CWL)) << 8 |
(5 + T(CL) - T(CWL));
timing[2] = (T(CWL) - 1) << 24 |
@@ -384,10 +384,10 @@ gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing)
(0x30 + T(CL)) << 24 |
(0xb + T(CL)) << 8 |
(T(CL) - 1);
- timing[4] = T(20) << 24 |
- T(21) << 16 |
- T(13) << 8 |
- T(13);
+ timing[4] = T(FAW) << 24 |
+ T(CKE) << 16 |
+ T(XPDLL) << 8 |
+ T(XPDLL);
timing[5] = T(RFC) << 24 |
max_t(u8,T(RCDRD), T(RCDWR)) << 16 |
max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 |
@@ -819,9 +819,9 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
unk718 |= 0x00000100;
if (next->bios.ramcfg_10_02_01)
unk71c |= 0x00000100;
- if (next->bios.timing_10_24 != 0xff) {
+ if (next->bios.timing_10_18 != 0xff) {
unk718 &= ~0xf0000000;
- unk718 |= next->bios.timing_10_24 << 28;
+ unk718 |= next->bios.timing_10_18 << 28;
}
if (next->bios.ramcfg_10_02_10)
r111100 &= ~0x04020000;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 87bde8f..54d37f3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -108,7 +108,7 @@ nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)
timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC));
timing[1] = (T(WR) + 1 + T(CWL)) << 24 |
- max_t(u8, T(18), 1) << 16 |
+ max_t(u8, T(12), 1) << 16 |
(T(WTR) + 1 + T(CWL)) << 8 |
(3 + T(CL) - T(CWL));
timing[2] = (T(CWL) - 1) << 24 |
@@ -120,8 +120,8 @@ nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing)
(T(CL) - 1) << 8 |
(T(CL) - 1);
timing[4] = (cur4 & 0xffff0000) |
- T(13) << 8 |
- T(13);
+ T(XPDLL) << 8 |
+ T(XPDLL);
timing[5] = T(RFC) << 24 |
max_t(u8, T(RCDRD), T(RCDWR)) << 16 |
T(RP);
--
2.9.3
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