On Thu, May 15, 2025 at 03:41:52PM +0200, PIERRE AUGIER via NumPy-Discussion
wrote:
> == PyPy HPy univ / CPy native (time ratio, smaller is better)
> ==
> TestModule::test_noargs 0.50
> TestModule::test_onearg_None 0.60
> TestModule::test_one
On Sun, May 18, 2025 at 9:40 AM Jerome Kieffer
wrote:
> Hi,
>
> First I would like to highlight that "X86_V2" is very specific to the
> implementation in numpy, basically this implies the support of all 128
> bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
> any 256bit SIMD
On Sun, May 18, 2025 at 10:39 AM Jerome Kieffer
wrote:
>
> Hi,
>
> First I would like to highlight that "X86_V2" is very specific to the
> implementation in numpy, basically this implies the support of all 128
> bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
> any 256bit SI
Hi Jerome,
`X86_V2` includes also `POPCNT CX16 LAHF` along with SSE4.2.
All CPUs that support `SSE4.2` also include these instructions.
I think Ralf is right to exclude servers in the case of using X86_V2 as a
baseline.
Basically, older servers that run architectures like Penryn (17 years ago)
or
Hi,
First I would like to highlight that "X86_V2" is very specific to the
implementation in numpy, basically this implies the support of all 128
bits SIMD extensions, i.e. SSE1,2,3&4, but does apparenty not requires
any 256bit SIMD (AVX).
Ralph, the stats you are using are made on end-user hardwa
