Not now, and not likely any time soon. ARM processors use CoreSight while MIPS
uses EJTAG. While Renesas H-UID is based on JTAG, the documentation does not
appear to be freely available, so the likelihood of OpenOCD ever supporting it
is quite slim.
From: Flemming Futtrup [mailto:f...@deif.com]
Le 17/01/2012 07:19, Flemming Futtrup a écrit :
>
> Hello Everybody,
>
> Thanks for all the cool work – OpenOCD is simply brilliant.
>
> We use it for multiple purposes:
>
> -Flashloading for HW people with little SW experience.
>
> -Debugging STM32 with OpenOCD+GDB+eclipse.
>
> Now to the business
This is done in the target implementation already.
On 17.01.2012 22:21, Uwe Bonnes wrote:
> Hello,
>
> at least for github/stlink a call to the equivalent function to
> src/jtag/drivers/stlink_usb.c:stlink_usb_write_mem8()
> with more than 64 bytes resulted in strange side effects.
> I propose yo
Hello,
at least for github/stlink a call to the equivalent function to
src/jtag/drivers/stlink_usb.c:stlink_usb_write_mem8()
with more than 64 bytes resulted in strange side effects.
I propose you check for the size and act appropriate.
Bye
--
Uwe Bonnesb...@elektron.ikp.physik.t
Am 01/17/2012 12:59 PM, schrieb jana1...@centrum.cz:
> So I found out TCK,TMS,TDO,TDI and RST signals on the JTAG connector
> on my PCB.
> The datasheet for the BCM7401 says the values for these are 3.3V.
> But I can not find Vcc/Vref on JTAG.
> Where should lead that Vcc/Vref from that JTAG conne
Hi,
Spencer Oliver wrote:
> On 17 January 2012 13:35, Jonathan Dumaresq
> wrote:
>>
>
> Does a stm32x mass erase succeed?
How Do I clear the Readout option with OpenOCD ?
Jonathan
>
> Cheers
> Spen
--
Keep Your D
> "Uwe" == Uwe Bonnes writes:
Uwe> Hello,
Uwe> did anybody program the STM32L1 via /src/flash/nor/stm32lx.c and
Uwe> the half_page algorithm successfully?
Uwe> (github)stlink loads the same code as
Uwe> /src/flash/nor/stm32lx.c:stm32lx_flash_write_code_16[] but as soon
Is this a custom hardware design/connector or a new jtag specification?
On 17.01.2012 18:56, jana1...@centrum.cz wrote:
> Does openOCD support EJTAG 2.0 standards?
> Thanks
>
>
>
> --
> Keep Your Developer Skills Curre
Does openOCD support EJTAG 2.0 standards?
Thanks
--
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Hello,
did anybody program the STM32L1 via /src/flash/nor/stm32lx.c and the
half_page algorithm successfully?
(github)stlink loads the same code as
/src/flash/nor/stm32lx.c:stm32lx_flash_write_code_16[]
but as soon as the code is executed, things go astray. The similar mechanisme
for the F1 work
This is an automated email from Gerrit.
Spencer Oliver (s...@spen-soft.co.uk) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/388
-- gerrit
commit 0852c88fb34acd2a077553cee7f4c1a6cc4e6223
Author: Spencer Oliver
Date: Tue Jan 17 16:04:53 2012 +
This is an automated email from Gerrit.
Spencer Oliver (s...@spen-soft.co.uk) just uploaded a new patch set to Gerrit,
which you can find at http://openocd.zylin.com/389
-- gerrit
commit 627892eb8675e69a41eb159b26f8f06a9da4eb49
Author: Spencer Oliver
Date: Tue Jan 17 16:05:44 2012 +
Hi,
Uwe Bonnes wrote:
>> "Spencer" == Spencer Oliver writes:
>
> ...
>
> Spencer> Looking at the datasheet it looks as if it uses the same
> flash Spencer> controller as stm32f1 (stm32f1x.c).
>
> What device are you talking about? What datasheet?
>
> I don't see any STM Cortex M0
Hi Spencer,
Spencer Oliver wrote:
> On 17 January 2012 13:35, Jonathan Dumaresq
> wrote:
>>
>> The stlinkV2. I got some of the protocol working but I could not get
>> the flash programmed. I can write to ram but could not get it work
>> with the flash.
>>
>> I try to disable the working area
> "Spencer" == Spencer Oliver writes:
...
Spencer> Looking at the datasheet it looks as if it uses the same flash
Spencer> controller as stm32f1 (stm32f1x.c).
What device are you talking about? What datasheet?
I don't see any STM Cortex M0 device yet. Have you more information?
Th
On 17 January 2012 13:35, Jonathan Dumaresq wrote:
>
> The stlinkV2. I got some of the protocol working but I could not get the
> flash programmed. I can write to ram but could not get it work with the
> flash.
>
> I try to disable the working area to have the jtag adapter to write directly
> thru
This is an automated email from Gerrit.
Timo Ketola (t...@exertus.fi) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/387
-- gerrit
commit 23092c9bccb6274945e87ef96b40c3484b7684f6
Author: Timo Ketola
Date: Tue Jan 17 16:10:10 2012 +0200
doc: Updat
Hello,
if you are able to write/read the ram you should be able to write the flash.
First you need to
figure out what you need to initialize before you are able to write the flash.
Maybe the flash is
locked or something else, check the flash status registers or other registers
to figure out wha
This is an automated email from Gerrit.
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-- gerrit
commit ec4685b75ba1d32d6e0bdbfcc5b03f76f8d94c67
Author: Spencer Oliver
Date: Tue Jan 17 13:39:46 2012 +
Hi,
Freddie Chopin wrote:
> Hi!
>
> M0 is not in OpenOCD, because - from what I know - most (all?)
> Cortex-M0 chips have SWD only (no JTAG), and OpenOCD still does not
> support SWD protocol.
With the Stlink-V2 the SWD is working.
But I don't know if the internal (the armv6) is well support
Spencer Oliver wrote:
> On 16 January 2012 19:10, Jonathan Dumaresq
> wrote:
>> Hi,
>>
>> I just dig into the openocd source code and I don't see any
>> information about the Armv6-M arch. Is there eny one here that have
>> use the cortex-m0 with openOCD ?
>>
>> The flash loader must be updated
Hello Everybody,
Thanks for all the cool work - OpenOCD is simply brilliant.
We use it for multiple purposes:
-Flashloading for HW people with little SW experience.
-Debugging STM32 with OpenOCD+GDB+eclipse.
Now to the business.
---
One of my colleagues is asking if someone ha
So I found out TCK,TMS,TDO,TDI and RST signals on the JTAG connector on my PCB.
The datasheet for the BCM7401 says the values for these are 3.3V.
But I can not find
Vcc/Vref on JTAG.
Where should lead that Vcc/Vref from that JTAG connector on PCB? Directly to
CPU?
And wha
Hi , Peter ,
Thank you for your reply.
I checked the website http://www.versaloon.com/
But which model shall I buy?
My JTAG on PCB is 14pins, and TCK,TMS,TDO,TDI and RST has 3.3V , datasheet says
Thank you for the reply
> jana1...@centrum.cz wrote:
> > No I have not tried it yet.
>
> Try it o
First message bounced, so here it goes again:
-- Forwarded message --
Date: Mon, 16 Jan 2012 22:52:19 +0200
From: Petri Laakso
To: openocd-devel@lists.sourceforge.net
Subject: OpenOCD on NetBSD (patch)
Hi
I was trying to build OpenOCD on NetBSD and ran into problem,
during "make
On 16 January 2012 19:10, Jonathan Dumaresq wrote:
> Hi,
>
> I just dig into the openocd source code and I don't see any information
> about the Armv6-M arch. Is there eny one here that have use the cortex-m0
> with openOCD ?
>
> The flash loader must be updated to have the cortex-m0 asm code work
On 16.01.2012 16:43, Øyvind Harboe wrote:
> please submit it to Gerrit for review. Read the file
> in openocd/HACKING for details.
Ok, thanks, did that. Sorry for not to read that file - I happened to read only
the website and PATCHES.txt.
One hiccup though:
$ git pull --rebase origin/master
fa
This is an automated email from Gerrit.
Timo Ketola (t...@exertus.fi) just uploaded a new patch set to Gerrit, which
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-- gerrit
commit 5ddac5a04ced9b2e21738d5d7feed6de086f1cdf
Author: Timo Ketola
Date: Tue Jan 17 10:47:11 2012 +0200
NAND: Misl
This is an automated email from Gerrit.
Timo Ketola (t...@exertus.fi) just uploaded a new patch set to Gerrit, which
you can find at http://openocd.zylin.com/384
-- gerrit
commit 79dc6eebc6691daf207d9b069267bd9da13851bb
Author: Timo Ketola
Date: Tue Jan 17 10:42:19 2012 +0200
i.MX25: Se
This is an automated email from Gerrit.
Timo Ketola (t...@exertus.fi) just uploaded a new patch set to Gerrit, which
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-- gerrit
commit 5da5a40b3846b3c76a160e76b47ad51f751dfe66
Author: Timo Ketola
Date: Tue Jan 17 10:36:02 2012 +0200
i.MX25: Ad
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