On 10/02/2012 3:55 AM, David Riley wrote:
> Hello all,
>
> I'm building a board with an FT4232 on board to support UART access of
> various devices and reprogramming of the onboard ARM. I'd like to use SWD
> instead of JTAG for the ARM if possible, but I'm having a hard time finding
> documenta
There are 3 solutions i know:
1.) always read 8bit (no alignment problems) but doesn't work on all targets
2.) allocate a local aligned buffer and copy it to dst after target access
3.) synchronize the alignment from local buffer address with the target address
or vice versa, is it
not possible g
Drasko ,
Thank you for your reply.
> and where can I find out mips_ejtag_enter_debug() function?
I meant in source code, where I can find out that
mips_ejtag_enter_debug() function.
>
> Find a EJTAG manual. It is a first hit on a Google. In Table 6-9 EJTAG
>
Mathias K. wrote:
> can you try a cast like this:
>
> (uint32_t *)(void *)dst
I think that works fine to silence the warning, but I that is just
sweeping the problem under the carpet. Better fix it right.
//Peter
--
Vi
Hello,
can you try a cast like this:
(uint32_t *)(void *)dst
This is also used in dsp563xx.c to cast from an uint8_t pointer to a uin32_t
pointer.
Regards,
Mathias
On 09.02.2012 18:51, Andrew Parlane wrote:
> Hi Peter,
>
> That's the same conclusion I came to, I just wanted to let the rel
Andrew Parlane wrote:
> Slightly confused as to how no one else has seen this yet, I guess it
> could be my toolchain being picky.
The nios2 may have stricter alignment requirements than more common
and larger architectures.
//Peter
-
Hi Peter,
That's the same conclusion I came to, I just wanted to let the relevant
people know of the issue.
Slightly confused as to how no one else has seen this yet, I guess it
could be my toolchain being picky.
Thanks,
Andy
On 09/02/2012 16:55, Peter Stuge wrote:
> Andrew Parlane wrote:
>>
This is an automated email from Gerrit.
Freddie Chopin (freddie.cho...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/440
-- gerrit
commit a8be281f89f2365f821509c36513be71b7b0ad15
Author: Freddie Chopin
Date: Thu Feb 9 18:37:05 2012 +0100
This is an automated email from Gerrit.
Freddie Chopin (freddie.cho...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/439
-- gerrit
commit 2d3a0e480b1def60455099b0aae7604b3ce70efc
Author: Freddie Chopin
Date: Thu Feb 9 17:50:42 2012 +0100
David Riley wrote:
> I'm building a board with an FT4232 on board to support UART access
> of various devices and reprogramming of the onboard ARM. I'd like
> to use SWD instead of JTAG for the ARM if possible, but I'm having
> a hard time finding documentation on how to hook up the 4232 so
> that
On Thu, Feb 9, 2012 at 2:40 PM, wrote:
> Hi,
> Thank you for your reply.
> MIPS CPU is Broadcom BCM 7401.
> I tested it further and found out that if HALT state,
> SDRAM provides only 0s( zeros).
> I think it is logical, because the internal processor system bus clock
> was stopped and SDRAM is
Hello all,
I'm building a board with an FT4232 on board to support UART access of various
devices and reprogramming of the onboard ARM. I'd like to use SWD instead of
JTAG for the ARM if possible, but I'm having a hard time finding documentation
on how to hook up the 4232 so that it will be su
Andrew Parlane wrote:
> I'm trying to compile openocd for the zy1000, using the current HEAD:
> f86986a9ef9ca863bad3bec5ffbdea748d011b40
>
> Unfortunately I'm getting an error during compilation. I should add
> that a few months ago I succeeded in building, and it is only since
> I pulled the last
I can read IDCODE, IMPCODE as well.
But can not make the CPU enter debug state
> On Thu, Feb 09, 2012 at 02:40:21PM +0100, jana1...@centrum.cz wrote:
> > Hi,
> > Thank you for your reply.
> > MIPS CPU is Broadcom BCM 7401.
> > I tested it further and found out that if HALT state,
> > SDRAM provi
On Thu, Feb 09, 2012 at 02:40:21PM +0100, jana1...@centrum.cz wrote:
> Hi,
> Thank you for your reply.
> MIPS CPU is Broadcom BCM 7401.
> I tested it further and found out that if HALT state,
> SDRAM provides only 0s( zeros).
> I think it is logical, because the internal processor system bus cloc
Hi,
Thank you for your reply.
MIPS CPU is Broadcom BCM 7401.
I tested it further and found out that if HALT state,
SDRAM provides only 0s( zeros).
I think it is logical, because the internal processor system bus clock
was stopped and SDRAM is not refreshed.
Or am I wrong?
I think DEBUG state wo
On Thu, Feb 09, 2012 at 01:43:55PM +0100, jana1...@centrum.cz wrote:
> I need to read data, from SDRAM of my device, via JTAG.
> Must I make my device enter Debug state or only Halt state?
> Or none is nescessary?
May well depend on the actual chip / board etc. I think you've been
asked at leas
I need to read data, from SDRAM of my device, via JTAG.
Must I make my device enter Debug state or only Halt state?
Or none is nescessary?
Thanks
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