On Samstag, 29. Mai 2021 12:58:05 CEST Marc Schink wrote: > Hi Tim, > > I'm wondering why the registers for RISC-V targets are invalid > (register cache) after halting the core. When I try to display the > > values for all registers with "reg" I get the following output: > > reg > > ===== RISC-V Registers > ... > The OpenOCD riscv fork behaves the same. Is there a good reason for > that?
I'm guessing the registers are not loaded on halt for performance reasons. It takes time to retrieve the complete register set, if you do it on each halt, it can slow down a debug session considerably. Especially if you're source- stepping with gdb, or with conditional watch or breakpoints. > > Best regards, > Marc
