This is an automated email from Gerrit.
Antony Pavlov (antonynpav...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/1972
-- gerrit
commit 0af092bf1f4090b3e0e01a73205ccaf876639bb0
Author: Antony Pavlov <antonynpav...@gmail.com>
Date: Wed Feb 26 00:16:58 2014 +0400
[RFC] [WIP] mips32: add gdb target description support
This commit is inspired by
commit 1255b18fc650193094666ba8afd2018089cc9794
Author: Spencer Oliver <s...@spen-soft.co.uk>
Date: Fri Sep 13 09:44:36 2013 +0100
armv7m: add gdb target description support
Change-Id: I75c3971fd0599d34ed49fb73975378b57f2a4af0
Signed-off-by: Antony Pavlov <antonynpav...@gmail.com>
Cc: Spencer Oliver <s...@spen-soft.co.uk>
Cc: Oleksij Rempel <li...@rempel-privat.de>
Cc: Paul Fertser <fercer...@gmail.com>
Cc: Salvador Arroyo <sarroyof...@yahoo.es>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 11f39fe..5df0390 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -39,67 +39,134 @@ static const char *mips_isa_strings[] = {
"MIPS32", "MIPS16e"
};
+#define MIPS32_GDB_DUMMY_FP_REG 1
+
+/*
+ * GDB registers
+ * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml
+ */
static const struct {
unsigned id;
const char *name;
-} mips32_regs[MIPS32NUMCOREREGS] = {
- { 0, "zero", },
- { 1, "at", },
- { 2, "v0", },
- { 3, "v1", },
- { 4, "a0", },
- { 5, "a1", },
- { 6, "a2", },
- { 7, "a3", },
- { 8, "t0", },
- { 9, "t1", },
- { 10, "t2", },
- { 11, "t3", },
- { 12, "t4", },
- { 13, "t5", },
- { 14, "t6", },
- { 15, "t7", },
- { 16, "s0", },
- { 17, "s1", },
- { 18, "s2", },
- { 19, "s3", },
- { 20, "s4", },
- { 21, "s5", },
- { 22, "s6", },
- { 23, "s7", },
- { 24, "t8", },
- { 25, "t9", },
- { 26, "k0", },
- { 27, "k1", },
- { 28, "gp", },
- { 29, "sp", },
- { 30, "fp", },
- { 31, "ra", },
-
- { 32, "status", },
- { 33, "lo", },
- { 34, "hi", },
- { 35, "badvaddr", },
- { 36, "cause", },
- { 37, "pc" },
+ enum reg_type type;
+ const char *group;
+ const char *feature;
+ int flag;
+} mips32_regs[] = {
+ { 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
+ { 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
+ { 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
+ { 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+
+ { 38, "GDB dummy f0", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 39, "GDB dummy f1", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 40, "GDB dummy f2", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 41, "GDB dummy f3", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 42, "GDB dummy f4", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 43, "GDB dummy f5", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 44, "GDB dummy f6", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 45, "GDB dummy f7", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 46, "GDB dummy f8", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 47, "GDB dummy f9", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 48, "GDB dummy f10", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 49, "GDB dummy f11", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 50, "GDB dummy f12", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 51, "GDB dummy f13", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 52, "GDB dummy f14", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 53, "GDB dummy f15", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 54, "GDB dummy f16", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 55, "GDB dummy f17", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 56, "GDB dummy f18", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 57, "GDB dummy f19", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 58, "GDB dummy f20", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 59, "GDB dummy f21", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 60, "GDB dummy f22", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 61, "GDB dummy f23", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 62, "GDB dummy f24", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 63, "GDB dummy f25", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 64, "GDB dummy f26", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 65, "GDB dummy f27", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 66, "GDB dummy f28", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 67, "GDB dummy f29", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 68, "GDB dummy f30", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 69, "GDB dummy f31", REG_TYPE_IEEE_SINGLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 70, "GDB dummy fcsr", REG_TYPE_INT, "float",
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 71, "GDB dummy fir", REG_TYPE_INT, "float",
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
};
-/* number of mips dummy fp regs fp0 - fp31 + fsr and fir
- * we also add 18 unknown registers to handle gdb requests */
-#define MIPS32NUMFPREGS (34 + 18)
+#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
-static struct reg mips32_gdb_dummy_fp_reg = {
- .name = "GDB dummy floating-point register",
- .value = mips32_gdb_dummy_fp_value,
- .dirty = 0,
- .valid = 1,
- .size = 32,
- .arch_info = NULL,
-};
-
static int mips32_get_core_reg(struct reg *reg)
{
int retval;
@@ -131,14 +198,14 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t
*buf)
return ERROR_OK;
}
-static int mips32_read_core_reg(struct target *target, int num)
+static int mips32_read_core_reg(struct target *target, unsigned int num)
{
uint32_t reg_value;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- if ((num < 0) || (num >= MIPS32NUMCOREREGS))
+ if (num >= MIPS32_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = mips32->core_regs[num];
@@ -149,14 +216,14 @@ static int mips32_read_core_reg(struct target *target,
int num)
return ERROR_OK;
}
-static int mips32_write_core_reg(struct target *target, int num)
+static int mips32_write_core_reg(struct target *target, unsigned int num)
{
uint32_t reg_value;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- if ((num < 0) || (num >= MIPS32NUMCOREREGS))
+ if (num >= MIPS32_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
@@ -173,25 +240,21 @@ int mips32_get_gdb_reg_list(struct target *target, struct
reg **reg_list[],
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- int i;
+ unsigned int i;
/* include floating point registers */
- *reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
+ *reg_list_size = MIPS32_NUM_REGS;
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
- for (i = 0; i < MIPS32NUMCOREREGS; i++)
+ for (i = 0; i < MIPS32_NUM_REGS; i++)
(*reg_list)[i] = &mips32->core_cache->reg_list[i];
- /* add dummy floating points regs */
- for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS);
i++)
- (*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
-
return ERROR_OK;
}
int mips32_save_context(struct target *target)
{
- int i;
+ unsigned int i;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
@@ -200,7 +263,7 @@ int mips32_save_context(struct target *target)
/* read core registers */
mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
mips32->read_core_reg(target, i);
}
@@ -210,13 +273,13 @@ int mips32_save_context(struct target *target)
int mips32_restore_context(struct target *target)
{
- int i;
+ unsigned int i;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (mips32->core_cache->reg_list[i].dirty)
mips32->write_core_reg(target, i);
}
@@ -249,15 +312,14 @@ struct reg_cache *mips32_build_reg_cache(struct target
*target)
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- int num_regs = MIPS32NUMCOREREGS;
+ int num_regs = MIPS32_NUM_REGS;
struct reg_cache **cache_p =
register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
struct mips32_core_reg *arch_info = malloc(sizeof(struct
mips32_core_reg) * num_regs);
+ struct reg_feature *feature;
int i;
- register_init_dummy(&mips32_gdb_dummy_fp_reg);
-
/* Build the process context cache */
cache->name = "mips32 registers";
cache->next = NULL;
@@ -273,11 +335,38 @@ struct reg_cache *mips32_build_reg_cache(struct target
*target)
reg_list[i].name = mips32_regs[i].name;
reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
+
+ if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
+ reg_list[i].value = mips32_gdb_dummy_fp_value;
+ reg_list[i].valid = 1;
+ reg_list[i].arch_info = NULL;
+ register_init_dummy(®_list[i]);
+ } else {
+ reg_list[i].value = calloc(1, 4);
+ reg_list[i].valid = 0;
+ reg_list[i].type = &mips32_reg_type;
+ reg_list[i].arch_info = &arch_info[i];
+
+ reg_list[i].reg_data_type = calloc(1, sizeof(struct
reg_data_type));
+ if (reg_list[i].reg_data_type)
+ reg_list[i].reg_data_type->type =
mips32_regs[i].type;
+ else
+ LOG_ERROR("unable to allocate reg type list");
+ }
+
reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
- reg_list[i].type = &mips32_reg_type;
- reg_list[i].arch_info = &arch_info[i];
+
+ reg_list[i].group = mips32_regs[i].group;
+ reg_list[i].number = i;
+ reg_list[i].exist = true;
+ reg_list[i].caller_save = true; /* gdb defaults to true */
+
+ feature = calloc(1, sizeof(struct reg_feature));
+ if (feature) {
+ feature->name = mips32_regs[i].feature;
+ reg_list[i].feature = feature;
+ } else
+ LOG_ERROR("unable to allocate feature list");
}
return cache;
@@ -345,8 +434,8 @@ int mips32_run_algorithm(struct target *target, int
num_mem_params,
struct mips32_algorithm *mips32_algorithm_info = arch_info;
enum mips32_isa_mode isa_mode = mips32->isa_mode;
- uint32_t context[MIPS32NUMCOREREGS];
- int i;
+ uint32_t context[MIPS32_NUM_REGS];
+ unsigned int i;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
@@ -365,20 +454,20 @@ int mips32_run_algorithm(struct target *target, int
num_mem_params,
}
/* refresh core register cache */
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
mips32->read_core_reg(target, i);
context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value,
0, 32);
}
- for (i = 0; i < num_mem_params; i++) {
+ for (i = 0; i < (unsigned int)num_mem_params; i++) {
retval = target_write_buffer(target, mem_params[i].address,
mem_params[i].size, mem_params[i].value);
if (retval != ERROR_OK)
return retval;
}
- for (i = 0; i < num_reg_params; i++) {
+ for (i = 0; i < (unsigned int)num_reg_params; i++) {
struct reg *reg = register_get_by_name(mips32->core_cache,
reg_params[i].reg_name, 0);
if (!reg) {
@@ -402,7 +491,7 @@ int mips32_run_algorithm(struct target *target, int
num_mem_params,
if (retval != ERROR_OK)
return retval;
- for (i = 0; i < num_mem_params; i++) {
+ for (i = 0; i < (unsigned int)num_mem_params; i++) {
if (mem_params[i].direction != PARAM_OUT) {
retval = target_read_buffer(target,
mem_params[i].address, mem_params[i].size,
mem_params[i].value);
@@ -411,7 +500,7 @@ int mips32_run_algorithm(struct target *target, int
num_mem_params,
}
}
- for (i = 0; i < num_reg_params; i++) {
+ for (i = 0; i < (unsigned int)num_reg_params; i++) {
if (reg_params[i].direction != PARAM_OUT) {
struct reg *reg =
register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
if (!reg) {
@@ -430,7 +519,7 @@ int mips32_run_algorithm(struct target *target, int
num_mem_params,
}
/* restore everything we saved before */
- for (i = 0; i < MIPS32NUMCOREREGS; i++) {
+ for (i = 0; i < MIPS32_NUM_REGS; i++) {
uint32_t regvalue;
regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value,
0, 32);
if (regvalue != context[i]) {
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 951b2ed..4d82d33 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -66,6 +66,7 @@
/* offsets into mips32 core register cache */
enum {
MIPS32_PC = 37,
+ MIPS32_FIR = 71,
MIPS32NUMCOREREGS
};
@@ -100,8 +101,8 @@ struct mips32_common {
struct mips32_comparator *data_break_list;
/* register cache to processor synchronization */
- int (*read_core_reg)(struct target *target, int num);
- int (*write_core_reg)(struct target *target, int num);
+ int (*read_core_reg)(struct target *target, unsigned int num);
+ int (*write_core_reg)(struct target *target, unsigned int num);
};
static inline struct mips32_common *
--
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