This is an automated email from Gerrit.

Spencer Oliver (s...@spen-soft.co.uk) just uploaded a new patch set to Gerrit, 
which you can find at http://openocd.zylin.com/1897

-- gerrit

commit 3470ec93b9907d5dbce858de76e8f9d389d8562b
Author: Spencer Oliver <s...@spen-soft.co.uk>
Date:   Fri Jan 24 12:43:41 2014 +0000

    doc: add missing reg command argument 'force'
    
    The argument 'force' enables a user to bypass the internal cache and read
    a target register directly. However it is missing from the user guide.
    
    Change-Id: I26f689eec20b38a0dc5294626b25df566b554446
    Signed-off-by: Spencer Oliver <s...@spen-soft.co.uk>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index d8c7ca1..8c30522 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6372,7 +6372,7 @@ various operations. The current target may be changed
 by using @command{targets} command with the name of the
 target which should become current.
 
-@deffn Command reg [(number|name) [value]]
+@deffn Command reg [(number|name) [value]] [force]
 Access a single register by @var{number} or by its @var{name}.
 The target must generally be halted before access to CPU core
 registers is allowed. Depending on the hardware, some other
@@ -6386,6 +6386,8 @@ which are also dirty (and will be written back later)
 are flagged as such.
 
 @emph{With number/name}: display that register's value.
+Use @var{force} argument to read directly from the target,
+bypassing any internal cache.
 
 @emph{With both number/name and value}: set register's value.
 Writes may be held in a writeback cache internal to OpenOCD,

-- 

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