This is an automated email from Gerrit.
Olivier Schonken (olivier.schon...@gmail.com) just uploaded a new patch set to
Gerrit, which you can find at http://openocd.zylin.com/2576
-- gerrit
commit 4d437dcb407a662e78f1032daf6f866a42c8062a
Author: Olivier Schonken <olivier.schon...@gmail.com>
Date: Thu Mar 5 11:00:24 2015 +0200
tcl/board: Add Atmel SAMA5D3_XPLAINED board
Tested with J-Link based Atmel SAM-ICE and atmel SAMA5d3_XPLAINED board
Change-Id: I6037ca70bdbc3ddecaa8a6fee3dd273542a34848
Signed-off-by: Olivier Schonken <olivier.schon...@gmail.com>
diff --git a/tcl/board/atmel_sama5d3_xplained_pro.cfg
b/tcl/board/atmel_sama5d3_xplained_pro.cfg
new file mode 100644
index 0000000..6965c6b
--- /dev/null
+++ b/tcl/board/atmel_sama5d3_xplained_pro.cfg
@@ -0,0 +1,233 @@
+################################################################################
+# Atmel SAMA5D3_Xplained_pro eval board
+################################################################################
+
+########################################
+# Known Issues with SAMA5DXX and openocd
+########################################
+#1. The JTAG circuitry is disabled at reset. Has something to do with their
+# secure boot ROM code.
+#2. To get OpenOCD to work with this board, the board must be started up in
+# SAM-BA mode with a USB device cable connected
+#3. The 'mon reset halt' and 'mon reset init' commands currently does not work
+# properly
+
+set CHIPNAME at91sama5d36
+
+reset_config trst_and_srst
+
+transport select jtag
+
+source [find mem_helper.tcl]
+source [find target/at91sama5dXX.cfg]
+
+# The SAMA5D3 has two SRAM areas, one starting at 0x00300000 and the other
starting at 0x00310000.
+# Both areas are 64 kB long.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000
-work-area-size 0x20000 -work-area-backup 1
+
+$_TARGETNAME configure -event gdb-attach { at91sama5d3_halt }
+$_TARGETNAME configure -event reset-init { at91sama5d3_ek_init }
+
+proc read_register {register} {
+ set result ""
+ mem2array result 32 $register 1
+ return $result(0)
+}
+
+proc at91sama5d3_halt { } {
+ halt
+}
+
+proc at91sama5d3_ek_init { } {
+ echo "Initializing Sama5d3"
+ adapter_khz 100
+ # First disable watchdog
+ mww 0xfffffe44 0x00008000
+ # WDT_MR : disable watchdog.
+ # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+
+ mww 0xfffffc20 0x00374009;# Keep RC oscillator enabled
+ while { [expr [read_register 0xfffffc68] & 0x00000001] == 0 } { sleep 1
}
+ mww 0xfffffc20 0x01374009;# Keep RC oscillator enabled
+ while { [expr [read_register 0xfffffc68] & 0x00010000] == 0 } { sleep 1
}
+ mww 0xfffffc20 0x01374001;# Disable RC oscillator
+
+ # Select main system clock. Set processor clock divide by 2 in PMC_MCKR.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00000001
+ while { [expr [read_register 0xfffffc68] & 0x08] == 0 } { sleep 1 }
+
+ # Set PLLA Register for 528 MHz (divider: bypass, multiplier: 43).
+ # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+ # PCK = 528MHz, MCK = 132MHz
+ mww 0xfffffc28 0x20ac3f01
+ while { [expr [read_register 0xfffffc68] & 0x02] == 0 } { sleep 1 }
+ #Initialize PLLA charge pump
+ mww 0xfffffc80 0x00000300
+
+ # Now change PMC_MCKR register to select PLLA.
+ # Wait for MCKRDY signal from PMC_SR to assert.
+
+ mww 0xfffffc30 0x00000202
+ while { [expr [read_register 0xfffffc68] & 0x08] == 0 } { sleep 1 }
+
+ # Processor and master clocks are now operating and stable at
following frequencies:
+ # -> MCLK = 133 MHz
+ # -> PCLK = 528 MHz
+ # Adaptive clocking not possible - no rtck connected on at91sama5d3X-ek
CM boards
+ # adapter_khz 0
+ # Enable faster DCC downloads and memory accesses.
+ ########################################################################
+ #Enabling DRAM
+ ########################################################################
+ #Enabling periph clock for MPDDR
+ mww 0xfffffd00 0x00020000
+ #enabling system clock
+ mww 0xfffffc00 0x00000004
+
+ # Init the special register for sama5d3x
+ # MPDDRC DLL Slave Offset Register: DDR2 configuration
+ mww 0xffffea78 0x01010001
+
+ # MPDDRC DLL Master Offset Register
+ # write master + clk90 offset
+ mww 0xffffea74 0xc5010107
+ # MPDDRC I/O Calibration Register
+ # DDR2 RZQ = 50 Ohm
+ # TZQIO = 4
+ mww 0xffffea34 0x00000404
+
+ # Now Start the DRAM init dance..
+ # 1. Program the memory device type into the Memory Device Register
+ mww 0xffffea20 0x00000006
+
+ # 2a. Program the feature of DDR2-SDRAM device into the Configuration
Register
+ mww 0xffffea08 0x00f20039
+ # 2b. Program the feature of DDR2-SDRAM device into the Timing Register
+ #TPR0
+ mww 0xffffea0c 0x22228226
+ #TPR1
+ mww 0xffffea10 0x02c81311
+ #TPR2
+ mww 0xffffea14 0x00062288
+
+ # 3. Next issue a 'NOP' command through the MPDDRC_MR register followed
by writing a zero value into
+ # the starting memory location for the SDRAM.
+ mww 0xffffea00 0x00000001
+ mww 0x20000000 0
+ sleep 1
+
+ # 4. An NOP command is issued to the DDR2-SDRAM
+ mww 0xffffea00 0x00000001
+ mww 0x20000000 0
+ sleep 1
+
+ # 5. An all banks precharge command is issued to the DDR2-SDRAM.
+ mww 0xffffea00 0x00000010
+ mww 0x20000000 0
+ sleep 1
+
+ # 6. An Extended Mode Register set(EMRS2) cycle is issued to chose
between commercial or high
+ # temperature operations.
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1] is set to 1 and BA[0]
is set to 0.
+
+ mww 0xffffea00 0x00000005
+ mww 0x20002000 0
+ sleep 1
+
+ # 7. An Extended Mode Register set(EMRS3) cycle is issued
+ # to set the Extended Mode Register to "0".
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1] is set to 1 and BA[0]
is set to 1.
+
+ mww 0xffffea00 0x00000005
+ mww 0x20003000 0
+ sleep 1
+
+ # 8. An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
+ # and to program D.I.C(Output Driver Impedance Control)
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1] is set to 0 and BA[0]
is set to 1.
+
+ mww 0xffffea00 0x00000005
+ mww 0x20001000 0
+ sleep 1
+
+ # 9. Program DLL field into the Configuration Register to high(Enable
DLL reset)
+ mww 0xffffea08 0x00f200b9
+
+ # 10. A Mode Register set(MRS) cycle is issied to reset DLL.
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1:0] bits are set to 0.
+
+ mww 0xffffea00 0x00000003
+ mww 0x20000000 0
+ sleep 1
+
+ # 11. An all banks precharge command is issued to the DDR2-SDRAM.
+ mww 0xffffea00 0x00000002
+ mww 0x20000000 0
+ sleep 1
+
+ # 12. 2 Auto-refresh commands
+ mww 0xffffea00 0x00000004
+ mww 0x20000000 0
+ sleep 1
+ mww 0xffffea00 0x00000004
+ mww 0x20000000 0
+ sleep 1
+
+ # 13. Program DLL field into the Configuration Register to low(Disable
DLL reset)
+ mww 0xffffea08 0x00f20039
+
+ # 14. A Mode Register set (MRS) cycle is issued to program
+ # the parameters of the DDR2-SDRAM devices, in particular CAS latency,
+ # burst length and to disable DDL reset.
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1:0] bits are set to 0.
+ mww 0xffffea00 0x00000003
+ mww 0x20000000 0
+ sleep 1
+
+ # 15. Program OCD field into the Configuration Register
+ # to high (OCD calibration default).
+ mww 0xffffea08 0x00f27039
+ sleep 1
+
+ # 16. An Extended Mode Register set (EMRS1) cycle is issued to OCD
default value.
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1] is set to 0 and BA[0]
is set to 1.
+ mww 0xffffea00 0x00000005
+ mww 0x20001000 0
+ sleep 1
+
+ #17. Program OCD field into the Configuration Register
+ # to low (OCD calibration mode exit).
+ mww 0xffffea08 0x00f20039
+ sleep 1
+
+ # 18. An Extended Mode Register set (EMRS1) cycle is issued to OCD
default value.
+ # Perform a write access to DDR2-SDRAM to acknowledge this command.
+ # The write address must be chosen so that BA[1] is set to 0 and BA[0]
is set to 1.
+ mww 0xffffea00 0x00000005
+ mww 0x20001000 0
+ sleep 1
+
+ # 19. A Nornal mode command is provided.
+ mww 0xffffea00 0x00000000
+ mww 0x20000000 0
+ # 20. Perform a write access to any DDR2-SDRAM address
+ mww 0x20000000 0
+
+ # 21. Write the refresh rate into the count field in the Refresh Timer
register.(Refresh timer: 7.8125us)
+ mww 0xffffea04 0x0000040f
+
+ # Now we are ready to work on the DDRSDR, wait for end of calibration
+ sleep 1
+ adapter_khz 1000
+ ########################################################################
+ #Enabling Nandflash
+ ########################################################################
+}
--
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